// !!!!!! This generated VQM is intended for Academic use or Internal Altera use only !!!!!!
// Functionality may not be correct on the programmed device or in simulation


// Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other 
// applicable license agreement, including, without limitation, 
// that your use is for the sole purpose of programming logic 
// devices manufactured by Altera and sold by Altera or its 
// authorized distributors.  Please refer to the applicable 
// agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus Prime"
// VERSION "Version 15.1.2 Build 193 02/01/2016 Patches 2.39 SJ Standard Edition"

// DATE "05/28/2021 19:07:45"

module 	float_add_function_wrapper (
    smack_clk,
    smack_sclk,
    smack_en,
    smack_scanin,
    smack_scanout,
	clock,
	resetn,
	local_router_hang,
	avs_cra_enable,
	avs_cra_read,
	avs_cra_write,
	avs_cra_address,
	avs_cra_writedata,
	avs_cra_byteenable,
	avs_cra_readdata,
	avs_cra_readdatavalid,
	cra_irq,
	avm_local_bb1_ld__inst0_enable,
	avm_local_bb1_ld__inst0_readdata,
	avm_local_bb1_ld__inst0_readdatavalid,
	avm_local_bb1_ld__inst0_waitrequest,
	avm_local_bb1_ld__inst0_address,
	avm_local_bb1_ld__inst0_read,
	avm_local_bb1_ld__inst0_write,
	avm_local_bb1_ld__inst0_writeack,
	avm_local_bb1_ld__inst0_writedata,
	avm_local_bb1_ld__inst0_byteenable,
	avm_local_bb1_ld__inst0_burstcount,
	avm_local_bb1_ld__u0_inst0_enable,
	avm_local_bb1_ld__u0_inst0_readdata,
	avm_local_bb1_ld__u0_inst0_readdatavalid,
	avm_local_bb1_ld__u0_inst0_waitrequest,
	avm_local_bb1_ld__u0_inst0_address,
	avm_local_bb1_ld__u0_inst0_read,
	avm_local_bb1_ld__u0_inst0_write,
	avm_local_bb1_ld__u0_inst0_writeack,
	avm_local_bb1_ld__u0_inst0_writedata,
	avm_local_bb1_ld__u0_inst0_byteenable,
	avm_local_bb1_ld__u0_inst0_burstcount,
	avm_local_bb1_st_c0_exe1_inst0_enable,
	avm_local_bb1_st_c0_exe1_inst0_readdata,
	avm_local_bb1_st_c0_exe1_inst0_readdatavalid,
	avm_local_bb1_st_c0_exe1_inst0_waitrequest,
	avm_local_bb1_st_c0_exe1_inst0_address,
	avm_local_bb1_st_c0_exe1_inst0_read,
	avm_local_bb1_st_c0_exe1_inst0_write,
	avm_local_bb1_st_c0_exe1_inst0_writeack,
	avm_local_bb1_st_c0_exe1_inst0_writedata,
	avm_local_bb1_st_c0_exe1_inst0_byteenable,
	avm_local_bb1_st_c0_exe1_inst0_burstcount);
input   smack_clk;
input   smack_sclk;
input   smack_en;
input   smack_scanin;
output  smack_scanout;
input 	clock;
input 	resetn;
input 	local_router_hang;
input 	avs_cra_enable;
input 	avs_cra_read;
input 	avs_cra_write;
input 	[3:0] avs_cra_address;
input 	[63:0] avs_cra_writedata;
input 	[7:0] avs_cra_byteenable;
output 	[63:0] avs_cra_readdata;
output 	avs_cra_readdatavalid;
output 	cra_irq;
output 	avm_local_bb1_ld__inst0_enable;
input 	[255:0] avm_local_bb1_ld__inst0_readdata;
input 	avm_local_bb1_ld__inst0_readdatavalid;
input 	avm_local_bb1_ld__inst0_waitrequest;
output 	[30:0] avm_local_bb1_ld__inst0_address;
output 	avm_local_bb1_ld__inst0_read;
output 	avm_local_bb1_ld__inst0_write;
input 	avm_local_bb1_ld__inst0_writeack;
output 	[255:0] avm_local_bb1_ld__inst0_writedata;
output 	[31:0] avm_local_bb1_ld__inst0_byteenable;
output 	[4:0] avm_local_bb1_ld__inst0_burstcount;
output 	avm_local_bb1_ld__u0_inst0_enable;
input 	[255:0] avm_local_bb1_ld__u0_inst0_readdata;
input 	avm_local_bb1_ld__u0_inst0_readdatavalid;
input 	avm_local_bb1_ld__u0_inst0_waitrequest;
output 	[30:0] avm_local_bb1_ld__u0_inst0_address;
output 	avm_local_bb1_ld__u0_inst0_read;
output 	avm_local_bb1_ld__u0_inst0_write;
input 	avm_local_bb1_ld__u0_inst0_writeack;
output 	[255:0] avm_local_bb1_ld__u0_inst0_writedata;
output 	[31:0] avm_local_bb1_ld__u0_inst0_byteenable;
output 	[4:0] avm_local_bb1_ld__u0_inst0_burstcount;
output 	avm_local_bb1_st_c0_exe1_inst0_enable;
input 	[255:0] avm_local_bb1_st_c0_exe1_inst0_readdata;
input 	avm_local_bb1_st_c0_exe1_inst0_readdatavalid;
input 	avm_local_bb1_st_c0_exe1_inst0_waitrequest;
output 	[30:0] avm_local_bb1_st_c0_exe1_inst0_address;
output 	avm_local_bb1_st_c0_exe1_inst0_read;
output 	avm_local_bb1_st_c0_exe1_inst0_write;
input 	avm_local_bb1_st_c0_exe1_inst0_writeack;
output 	[255:0] avm_local_bb1_st_c0_exe1_inst0_writedata;
output 	[31:0] avm_local_bb1_st_c0_exe1_inst0_byteenable;
output 	[4:0] avm_local_bb1_st_c0_exe1_inst0_burstcount;
wire \local_router_hang~input0 ;
wire \avs_cra_enable~input0 ;
wire \avm_local_bb1_ld__inst0_writeack~input0 ;
wire \avm_local_bb1_ld__u0_inst0_writeack~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[0]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[1]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[2]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[3]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[4]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[5]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[6]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[7]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[8]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[9]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[10]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[11]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[12]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[13]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[14]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[15]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[16]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[17]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[18]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[19]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[20]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[21]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[22]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[23]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[24]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[25]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[26]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[27]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[28]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[29]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[30]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[31]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[32]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[33]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[34]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[35]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[36]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[37]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[38]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[39]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[40]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[41]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[42]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[43]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[44]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[45]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[46]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[47]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[48]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[49]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[50]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[51]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[52]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[53]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[54]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[55]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[56]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[57]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[58]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[59]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[60]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[61]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[62]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[63]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[64]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[65]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[66]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[67]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[68]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[69]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[70]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[71]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[72]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[73]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[74]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[75]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[76]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[77]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[78]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[79]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[80]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[81]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[82]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[83]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[84]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[85]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[86]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[87]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[88]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[89]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[90]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[91]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[92]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[93]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[94]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[95]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[96]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[97]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[98]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[99]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[100]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[101]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[102]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[103]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[104]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[105]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[106]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[107]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[108]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[109]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[110]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[111]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[112]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[113]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[114]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[115]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[116]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[117]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[118]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[119]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[120]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[121]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[122]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[123]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[124]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[125]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[126]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[127]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[128]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[129]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[130]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[131]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[132]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[133]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[134]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[135]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[136]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[137]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[138]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[139]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[140]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[141]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[142]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[143]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[144]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[145]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[146]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[147]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[148]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[149]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[150]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[151]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[152]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[153]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[154]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[155]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[156]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[157]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[158]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[159]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[160]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[161]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[162]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[163]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[164]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[165]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[166]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[167]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[168]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[169]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[170]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[171]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[172]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[173]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[174]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[175]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[176]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[177]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[178]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[179]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[180]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[181]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[182]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[183]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[184]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[185]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[186]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[187]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[188]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[189]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[190]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[191]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[192]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[193]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[194]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[195]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[196]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[197]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[198]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[199]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[200]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[201]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[202]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[203]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[204]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[205]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[206]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[207]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[208]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[209]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[210]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[211]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[212]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[213]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[214]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[215]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[216]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[217]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[218]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[219]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[220]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[221]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[222]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[223]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[224]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[225]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[226]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[227]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[228]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[229]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[230]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[231]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[232]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[233]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[234]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[235]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[236]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[237]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[238]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[239]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[240]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[241]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[242]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[243]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[244]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[245]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[246]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[247]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[248]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[249]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[250]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[251]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[252]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[253]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[254]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdata[255]~input0 ;
wire \avm_local_bb1_st_c0_exe1_inst0_readdatavalid~input0 ;
wire \clock~input0 ;
wire \clock~CLKENA0 ;
wire \avs_cra_address[1]~input0 ;
wire \avs_cra_address[2]~input0 ;
wire \avs_cra_address[0]~input0 ;
wire \avs_cra_address[3]~input0 ;
wire \WideOr1~0 ;
wire \avs_cra_write~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder ;
wire \resetn~input0 ;
wire \resetn~CLKENA0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2 ;
wire \avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ;
wire \avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ;
wire \avs_cra_writedata[13]~input0 ;
wire \avs_cra_byteenable[1]~input0 ;
wire \local_size_NO_SHIFT_REG[0][8]~6 ;
wire \local_size_NO_SHIFT_REG[0][13] ;
wire \avs_cra_writedata[12]~input0 ;
wire \local_size_NO_SHIFT_REG[0][12] ;
wire \avs_cra_writedata[11]~input0 ;
wire \local_size_NO_SHIFT_REG[0][11]~feeder ;
wire \local_size_NO_SHIFT_REG[0][11] ;
wire \avs_cra_writedata[10]~input0 ;
wire \local_size_NO_SHIFT_REG[0][10] ;
wire \avs_cra_writedata[9]~input0 ;
wire \local_size_NO_SHIFT_REG[0][9]~feeder ;
wire \local_size_NO_SHIFT_REG[0][9] ;
wire \avs_cra_writedata[8]~input0 ;
wire \local_size_NO_SHIFT_REG[0][8]~feeder ;
wire \local_size_NO_SHIFT_REG[0][8] ;
wire \avs_cra_writedata[7]~input0 ;
wire \local_size_NO_SHIFT_REG[0][7]~feeder ;
wire \avs_cra_byteenable[0]~input0 ;
wire \local_size_NO_SHIFT_REG[0][0]~1 ;
wire \local_size_NO_SHIFT_REG[0][7] ;
wire \avs_cra_writedata[6]~input0 ;
wire \local_size_NO_SHIFT_REG[0][6] ;
wire \avs_cra_writedata[5]~input0 ;
wire \local_size_NO_SHIFT_REG[0][5]~feeder ;
wire \local_size_NO_SHIFT_REG[0][5] ;
wire \avs_cra_writedata[4]~input0 ;
wire \local_size_NO_SHIFT_REG[0][4] ;
wire \avs_cra_writedata[3]~input0 ;
wire \local_size_NO_SHIFT_REG[0][3] ;
wire \avs_cra_writedata[2]~input0 ;
wire \local_size_NO_SHIFT_REG[0][2]~feeder ;
wire \local_size_NO_SHIFT_REG[0][2] ;
wire \avs_cra_writedata[1]~input0 ;
wire \local_size_NO_SHIFT_REG[0][1] ;
wire \avs_cra_writedata[0]~input0 ;
wire \local_size_NO_SHIFT_REG[0][0]~feeder ;
wire \local_size_NO_SHIFT_REG[0][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1 ;
wire \avs_cra_writedata[31]~input0 ;
wire \local_size_NO_SHIFT_REG[0][31]~feeder ;
wire \avs_cra_byteenable[3]~input0 ;
wire \local_size_NO_SHIFT_REG[0][24]~8 ;
wire \local_size_NO_SHIFT_REG[0][31] ;
wire \avs_cra_writedata[30]~input0 ;
wire \local_size_NO_SHIFT_REG[0][30] ;
wire \avs_cra_writedata[29]~input0 ;
wire \local_size_NO_SHIFT_REG[0][29]~feeder ;
wire \local_size_NO_SHIFT_REG[0][29] ;
wire \avs_cra_writedata[28]~input0 ;
wire \local_size_NO_SHIFT_REG[0][28] ;
wire \avs_cra_writedata[27]~input0 ;
wire \local_size_NO_SHIFT_REG[0][27] ;
wire \avs_cra_writedata[26]~input0 ;
wire \local_size_NO_SHIFT_REG[0][26] ;
wire \avs_cra_writedata[25]~input0 ;
wire \local_size_NO_SHIFT_REG[0][25] ;
wire \avs_cra_writedata[24]~input0 ;
wire \local_size_NO_SHIFT_REG[0][24] ;
wire \avs_cra_writedata[23]~input0 ;
wire \local_size_NO_SHIFT_REG[0][23]~feeder ;
wire \avs_cra_byteenable[2]~input0 ;
wire \local_size_NO_SHIFT_REG[0][16]~7 ;
wire \local_size_NO_SHIFT_REG[0][23] ;
wire \avs_cra_writedata[22]~input0 ;
wire \local_size_NO_SHIFT_REG[0][22]~feeder ;
wire \local_size_NO_SHIFT_REG[0][22] ;
wire \avs_cra_writedata[21]~input0 ;
wire \local_size_NO_SHIFT_REG[0][21] ;
wire \avs_cra_writedata[20]~input0 ;
wire \local_size_NO_SHIFT_REG[0][20]~feeder ;
wire \local_size_NO_SHIFT_REG[0][20] ;
wire \avs_cra_writedata[19]~input0 ;
wire \local_size_NO_SHIFT_REG[0][19] ;
wire \avs_cra_writedata[18]~input0 ;
wire \local_size_NO_SHIFT_REG[0][18]~feeder ;
wire \local_size_NO_SHIFT_REG[0][18] ;
wire \avs_cra_writedata[17]~input0 ;
wire \local_size_NO_SHIFT_REG[0][17] ;
wire \avs_cra_writedata[16]~input0 ;
wire \local_size_NO_SHIFT_REG[0][16]~feeder ;
wire \local_size_NO_SHIFT_REG[0][16] ;
wire \avs_cra_writedata[15]~input0 ;
wire \local_size_NO_SHIFT_REG[0][15] ;
wire \avs_cra_writedata[14]~input0 ;
wire \local_size_NO_SHIFT_REG[0][14]~feeder ;
wire \local_size_NO_SHIFT_REG[0][14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13 ;
wire \avs_cra_writedata[32]~input0 ;
wire \avs_cra_byteenable[4]~input0 ;
wire \local_size_NO_SHIFT_REG[1][0]~2 ;
wire \local_size_NO_SHIFT_REG[1][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0] ;
wire \avs_cra_writedata[34]~input0 ;
wire \local_size_NO_SHIFT_REG[1][2] ;
wire \avs_cra_writedata[33]~input0 ;
wire \local_size_NO_SHIFT_REG[1][1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2] ;
wire \avs_cra_writedata[44]~input0 ;
wire \avs_cra_byteenable[5]~input0 ;
wire \local_size_NO_SHIFT_REG[1][8]~9 ;
wire \local_size_NO_SHIFT_REG[1][12] ;
wire \avs_cra_writedata[43]~input0 ;
wire \local_size_NO_SHIFT_REG[1][11]~feeder ;
wire \local_size_NO_SHIFT_REG[1][11] ;
wire \avs_cra_writedata[42]~input0 ;
wire \local_size_NO_SHIFT_REG[1][10]~feeder ;
wire \local_size_NO_SHIFT_REG[1][10] ;
wire \avs_cra_writedata[41]~input0 ;
wire \local_size_NO_SHIFT_REG[1][9] ;
wire \avs_cra_writedata[40]~input0 ;
wire \local_size_NO_SHIFT_REG[1][8]~feeder ;
wire \local_size_NO_SHIFT_REG[1][8] ;
wire \avs_cra_writedata[39]~input0 ;
wire \local_size_NO_SHIFT_REG[1][7]~feeder ;
wire \local_size_NO_SHIFT_REG[1][7] ;
wire \avs_cra_writedata[38]~input0 ;
wire \local_size_NO_SHIFT_REG[1][6] ;
wire \avs_cra_writedata[37]~input0 ;
wire \local_size_NO_SHIFT_REG[1][5]~feeder ;
wire \local_size_NO_SHIFT_REG[1][5] ;
wire \avs_cra_writedata[36]~input0 ;
wire \local_size_NO_SHIFT_REG[1][4]~feeder ;
wire \local_size_NO_SHIFT_REG[1][4] ;
wire \avs_cra_writedata[35]~input0 ;
wire \local_size_NO_SHIFT_REG[1][3]~feeder ;
wire \local_size_NO_SHIFT_REG[1][3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11] ;
wire \avs_cra_writedata[45]~input0 ;
wire \local_size_NO_SHIFT_REG[1][13]~feeder ;
wire \local_size_NO_SHIFT_REG[1][13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2 ;
wire \avs_cra_writedata[53]~input0 ;
wire \local_size_NO_SHIFT_REG[1][21]~feeder ;
wire \avs_cra_byteenable[6]~input0 ;
wire \local_size_NO_SHIFT_REG[1][16]~10 ;
wire \local_size_NO_SHIFT_REG[1][21] ;
wire \avs_cra_writedata[52]~input0 ;
wire \local_size_NO_SHIFT_REG[1][20] ;
wire \avs_cra_writedata[51]~input0 ;
wire \local_size_NO_SHIFT_REG[1][19] ;
wire \avs_cra_writedata[50]~input0 ;
wire \local_size_NO_SHIFT_REG[1][18] ;
wire \avs_cra_writedata[49]~input0 ;
wire \local_size_NO_SHIFT_REG[1][17]~feeder ;
wire \local_size_NO_SHIFT_REG[1][17] ;
wire \avs_cra_writedata[48]~input0 ;
wire \local_size_NO_SHIFT_REG[1][16] ;
wire \avs_cra_writedata[47]~input0 ;
wire \local_size_NO_SHIFT_REG[1][15]~feeder ;
wire \local_size_NO_SHIFT_REG[1][15] ;
wire \avs_cra_writedata[46]~input0 ;
wire \local_size_NO_SHIFT_REG[1][14]~feeder ;
wire \local_size_NO_SHIFT_REG[1][14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21] ;
wire \avs_cra_writedata[63]~input0 ;
wire \avs_cra_byteenable[7]~input0 ;
wire \local_size_NO_SHIFT_REG[1][24]~11 ;
wire \local_size_NO_SHIFT_REG[1][31] ;
wire \avs_cra_writedata[62]~input0 ;
wire \local_size_NO_SHIFT_REG[1][30]~feeder ;
wire \local_size_NO_SHIFT_REG[1][30] ;
wire \avs_cra_writedata[61]~input0 ;
wire \local_size_NO_SHIFT_REG[1][29] ;
wire \avs_cra_writedata[60]~input0 ;
wire \local_size_NO_SHIFT_REG[1][28] ;
wire \avs_cra_writedata[59]~input0 ;
wire \local_size_NO_SHIFT_REG[1][27] ;
wire \avs_cra_writedata[58]~input0 ;
wire \local_size_NO_SHIFT_REG[1][26] ;
wire \avs_cra_writedata[57]~input0 ;
wire \local_size_NO_SHIFT_REG[1][25]~feeder ;
wire \local_size_NO_SHIFT_REG[1][25] ;
wire \avs_cra_writedata[56]~input0 ;
wire \local_size_NO_SHIFT_REG[1][24] ;
wire \avs_cra_writedata[55]~input0 ;
wire \local_size_NO_SHIFT_REG[1][23]~feeder ;
wire \local_size_NO_SHIFT_REG[1][23] ;
wire \avs_cra_writedata[54]~input0 ;
wire \local_size_NO_SHIFT_REG[1][22]~feeder ;
wire \local_size_NO_SHIFT_REG[1][22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12 ;
wire \local_size_NO_SHIFT_REG[2][6]~feeder ;
wire \local_size_NO_SHIFT_REG[2][0]~0 ;
wire \local_size_NO_SHIFT_REG[2][6] ;
wire \local_size_NO_SHIFT_REG[2][5]~feeder ;
wire \local_size_NO_SHIFT_REG[2][5] ;
wire \local_size_NO_SHIFT_REG[2][4]~feeder ;
wire \local_size_NO_SHIFT_REG[2][4] ;
wire \local_size_NO_SHIFT_REG[2][3] ;
wire \local_size_NO_SHIFT_REG[2][2] ;
wire \local_size_NO_SHIFT_REG[2][1] ;
wire \local_size_NO_SHIFT_REG[2][0]~feeder ;
wire \local_size_NO_SHIFT_REG[2][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49 ;
wire \local_size_NO_SHIFT_REG[2][25]~feeder ;
wire \local_size_NO_SHIFT_REG[2][24]~5 ;
wire \local_size_NO_SHIFT_REG[2][25] ;
wire \local_size_NO_SHIFT_REG[2][24] ;
wire \local_size_NO_SHIFT_REG[2][23]~feeder ;
wire \local_size_NO_SHIFT_REG[2][16]~4 ;
wire \local_size_NO_SHIFT_REG[2][23] ;
wire \local_size_NO_SHIFT_REG[2][22]~feeder ;
wire \local_size_NO_SHIFT_REG[2][22] ;
wire \local_size_NO_SHIFT_REG[2][21] ;
wire \local_size_NO_SHIFT_REG[2][20]~feeder ;
wire \local_size_NO_SHIFT_REG[2][20] ;
wire \local_size_NO_SHIFT_REG[2][19]~feeder ;
wire \local_size_NO_SHIFT_REG[2][19] ;
wire \local_size_NO_SHIFT_REG[2][18]~feeder ;
wire \local_size_NO_SHIFT_REG[2][18] ;
wire \local_size_NO_SHIFT_REG[2][17] ;
wire \local_size_NO_SHIFT_REG[2][16] ;
wire \local_size_NO_SHIFT_REG[2][8]~3 ;
wire \local_size_NO_SHIFT_REG[2][15] ;
wire \local_size_NO_SHIFT_REG[2][14] ;
wire \local_size_NO_SHIFT_REG[2][13] ;
wire \local_size_NO_SHIFT_REG[2][12]~feeder ;
wire \local_size_NO_SHIFT_REG[2][12] ;
wire \local_size_NO_SHIFT_REG[2][11]~feeder ;
wire \local_size_NO_SHIFT_REG[2][11] ;
wire \local_size_NO_SHIFT_REG[2][10] ;
wire \local_size_NO_SHIFT_REG[2][9] ;
wire \local_size_NO_SHIFT_REG[2][8]~feeder ;
wire \local_size_NO_SHIFT_REG[2][8] ;
wire \local_size_NO_SHIFT_REG[2][7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20] ;
wire \local_size_NO_SHIFT_REG[2][26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21] ;
wire \local_size_NO_SHIFT_REG[2][31] ;
wire \local_size_NO_SHIFT_REG[2][30] ;
wire \local_size_NO_SHIFT_REG[2][29]~feeder ;
wire \local_size_NO_SHIFT_REG[2][29] ;
wire \local_size_NO_SHIFT_REG[2][28] ;
wire \local_size_NO_SHIFT_REG[2][27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~118 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~122 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~126 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~86 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~COUT ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ;
wire \num_groups_NO_SHIFT_REG[0][30]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][24]~5 ;
wire \num_groups_NO_SHIFT_REG[0][30] ;
wire \num_groups_NO_SHIFT_REG[0][29]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][29] ;
wire \num_groups_NO_SHIFT_REG[0][28]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][28] ;
wire \num_groups_NO_SHIFT_REG[0][27] ;
wire \num_groups_NO_SHIFT_REG[0][26] ;
wire \num_groups_NO_SHIFT_REG[0][25]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][25] ;
wire \num_groups_NO_SHIFT_REG[0][24]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][24] ;
wire \num_groups_NO_SHIFT_REG[0][16]~3 ;
wire \num_groups_NO_SHIFT_REG[0][23] ;
wire \num_groups_NO_SHIFT_REG[0][22]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][22] ;
wire \num_groups_NO_SHIFT_REG[0][21] ;
wire \num_groups_NO_SHIFT_REG[0][20]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][20] ;
wire \num_groups_NO_SHIFT_REG[0][19] ;
wire \num_groups_NO_SHIFT_REG[0][18]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][18] ;
wire \num_groups_NO_SHIFT_REG[0][17]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][17] ;
wire \num_groups_NO_SHIFT_REG[0][16] ;
wire \num_groups_NO_SHIFT_REG[0][15]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][8]~4 ;
wire \num_groups_NO_SHIFT_REG[0][15] ;
wire \num_groups_NO_SHIFT_REG[0][14] ;
wire \num_groups_NO_SHIFT_REG[0][13]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][13] ;
wire \num_groups_NO_SHIFT_REG[0][12]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][12] ;
wire \num_groups_NO_SHIFT_REG[0][11]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][11] ;
wire \num_groups_NO_SHIFT_REG[0][10]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][10] ;
wire \num_groups_NO_SHIFT_REG[0][9] ;
wire \num_groups_NO_SHIFT_REG[0][8]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][8] ;
wire \num_groups_NO_SHIFT_REG[0][0]~0 ;
wire \num_groups_NO_SHIFT_REG[0][7] ;
wire \num_groups_NO_SHIFT_REG[0][6] ;
wire \num_groups_NO_SHIFT_REG[0][5] ;
wire \num_groups_NO_SHIFT_REG[0][4]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][4] ;
wire \num_groups_NO_SHIFT_REG[0][3]~feeder ;
wire \num_groups_NO_SHIFT_REG[0][3] ;
wire \num_groups_NO_SHIFT_REG[0][2] ;
wire \num_groups_NO_SHIFT_REG[0][1] ;
wire \num_groups_NO_SHIFT_REG[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~82 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30] ;
wire \num_groups_NO_SHIFT_REG[0][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~125 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~78 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add3~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[0][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add0~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal0~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][15] ;
wire \num_groups_NO_SHIFT_REG[1][8]~7 ;
wire \num_groups_NO_SHIFT_REG[1][15] ;
wire \num_groups_NO_SHIFT_REG[1][14] ;
wire \num_groups_NO_SHIFT_REG[1][13] ;
wire \num_groups_NO_SHIFT_REG[1][12]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][12] ;
wire \num_groups_NO_SHIFT_REG[1][11]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][11] ;
wire \num_groups_NO_SHIFT_REG[1][10] ;
wire \num_groups_NO_SHIFT_REG[1][9] ;
wire \num_groups_NO_SHIFT_REG[1][8]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][8] ;
wire \num_groups_NO_SHIFT_REG[1][0]~1 ;
wire \num_groups_NO_SHIFT_REG[1][7] ;
wire \num_groups_NO_SHIFT_REG[1][6]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][6] ;
wire \num_groups_NO_SHIFT_REG[1][5]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][5] ;
wire \num_groups_NO_SHIFT_REG[1][4]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][4] ;
wire \num_groups_NO_SHIFT_REG[1][3] ;
wire \num_groups_NO_SHIFT_REG[1][2] ;
wire \num_groups_NO_SHIFT_REG[1][1] ;
wire \num_groups_NO_SHIFT_REG[1][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15] ;
wire \num_groups_NO_SHIFT_REG[1][16]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][16]~6 ;
wire \num_groups_NO_SHIFT_REG[1][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~125 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~78 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add4~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][31] ;
wire \num_groups_NO_SHIFT_REG[1][31]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][24]~8 ;
wire \num_groups_NO_SHIFT_REG[1][31] ;
wire \num_groups_NO_SHIFT_REG[1][30]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][30] ;
wire \num_groups_NO_SHIFT_REG[1][29]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][29] ;
wire \num_groups_NO_SHIFT_REG[1][28] ;
wire \num_groups_NO_SHIFT_REG[1][27] ;
wire \num_groups_NO_SHIFT_REG[1][26] ;
wire \num_groups_NO_SHIFT_REG[1][25]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][25] ;
wire \num_groups_NO_SHIFT_REG[1][24] ;
wire \num_groups_NO_SHIFT_REG[1][23]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][23] ;
wire \num_groups_NO_SHIFT_REG[1][22] ;
wire \num_groups_NO_SHIFT_REG[1][21] ;
wire \num_groups_NO_SHIFT_REG[1][20]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][20] ;
wire \num_groups_NO_SHIFT_REG[1][19]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][19] ;
wire \num_groups_NO_SHIFT_REG[1][18]~feeder ;
wire \num_groups_NO_SHIFT_REG[1][18] ;
wire \num_groups_NO_SHIFT_REG[1][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~82 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add1~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal1~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE ;
wire \num_groups_NO_SHIFT_REG[2][17]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][16]~9 ;
wire \num_groups_NO_SHIFT_REG[2][17] ;
wire \num_groups_NO_SHIFT_REG[2][16] ;
wire \num_groups_NO_SHIFT_REG[2][8]~10 ;
wire \num_groups_NO_SHIFT_REG[2][15] ;
wire \num_groups_NO_SHIFT_REG[2][14]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][14] ;
wire \num_groups_NO_SHIFT_REG[2][13] ;
wire \num_groups_NO_SHIFT_REG[2][12] ;
wire \num_groups_NO_SHIFT_REG[2][11]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][11] ;
wire \num_groups_NO_SHIFT_REG[2][10] ;
wire \num_groups_NO_SHIFT_REG[2][9] ;
wire \num_groups_NO_SHIFT_REG[2][8]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][8] ;
wire \num_groups_NO_SHIFT_REG[2][7]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][0]~2 ;
wire \num_groups_NO_SHIFT_REG[2][7] ;
wire \num_groups_NO_SHIFT_REG[2][6] ;
wire \num_groups_NO_SHIFT_REG[2][5]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][5] ;
wire \num_groups_NO_SHIFT_REG[2][4]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][4] ;
wire \num_groups_NO_SHIFT_REG[2][3]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][3] ;
wire \num_groups_NO_SHIFT_REG[2][2]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][2] ;
wire \num_groups_NO_SHIFT_REG[2][1]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][1] ;
wire \num_groups_NO_SHIFT_REG[2][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~125 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~126 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][28] ;
wire \num_groups_NO_SHIFT_REG[2][28]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][24]~11 ;
wire \num_groups_NO_SHIFT_REG[2][28] ;
wire \num_groups_NO_SHIFT_REG[2][27]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][27] ;
wire \num_groups_NO_SHIFT_REG[2][26]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][26] ;
wire \num_groups_NO_SHIFT_REG[2][25] ;
wire \num_groups_NO_SHIFT_REG[2][24] ;
wire \num_groups_NO_SHIFT_REG[2][23] ;
wire \num_groups_NO_SHIFT_REG[2][22] ;
wire \num_groups_NO_SHIFT_REG[2][21] ;
wire \num_groups_NO_SHIFT_REG[2][20] ;
wire \num_groups_NO_SHIFT_REG[2][19]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][19] ;
wire \num_groups_NO_SHIFT_REG[2][18]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~118 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~122 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~82 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14] ;
wire \num_groups_NO_SHIFT_REG[2][29]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~86 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~78 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add5~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][31] ;
wire \num_groups_NO_SHIFT_REG[2][31] ;
wire \num_groups_NO_SHIFT_REG[2][30]~feeder ;
wire \num_groups_NO_SHIFT_REG[2][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~121 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add2~117 ;
wire \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|Equal2~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|started~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|started ;
wire \acl_work_group_dispatcher:group_dispatcher|delayed_start~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|delayed_start ;
wire \acl_work_group_dispatcher:group_dispatcher|valid_out[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~2 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~2 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~3 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~30 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~30 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~31 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~34 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~35 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~38 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~39 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~34 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~38 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~22 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~22 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~23 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~26 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~26 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~27 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~18 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~18 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~19 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~14 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~10 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~14 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~15 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~10 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~11 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG ;
wire \acl_id_iterator:id_iter_inst0|issue~0 ;
wire \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0 ;
wire \acl_id_iterator:id_iter_inst0|just_seen_last_in_group ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~COUT ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0~COMBOUT ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~114 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~109 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~110 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~69 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~70 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~17 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~18 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~73 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~74 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~57 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~58 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~62 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~65 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~66 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~46 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~50 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~54 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~34 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~38 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~42 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~21 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~22 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~25 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~26 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~30 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~90 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~93 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~94 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~98 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~101 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~102 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~106 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~78 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~82 ;
wire \acl_work_group_dispatcher:group_dispatcher|Add6~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~115 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~114 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~110 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~111 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~70 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~71 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~15 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~19 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~75 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~74 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~59 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~58 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~63 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~62 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~66 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~67 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~46 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~47 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~50 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~51 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~55 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~54 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~35 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~34 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~39 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~38 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~43 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~42 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~23 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~27 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~31 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~30 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][21]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~91 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~90 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~94 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~95 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~99 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~98 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][24]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~103 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~102 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~107 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~106 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~79 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~78 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~83 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~82 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][28]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][23]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][22]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][2]~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][1]~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][0]~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][6]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][9]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][10]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][12]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][15]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][16]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][17]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][19]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][20]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][27]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][26]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][18]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][14]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][13]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][11]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][8]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][7]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][5]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][4]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ;
wire \kernel_arguments_NO_SHIFT_REG[138]~7 ;
wire \kernel_arguments_NO_SHIFT_REG[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21 ;
wire \kernel_arguments_NO_SHIFT_REG[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13 ;
wire \kernel_arguments_NO_SHIFT_REG[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17 ;
wire \kernel_arguments_NO_SHIFT_REG[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5 ;
wire \kernel_arguments_NO_SHIFT_REG[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9 ;
wire \kernel_arguments_NO_SHIFT_REG[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33 ;
wire \kernel_arguments_NO_SHIFT_REG[144]~6 ;
wire \kernel_arguments_NO_SHIFT_REG[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37 ;
wire \kernel_arguments_NO_SHIFT_REG[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41 ;
wire \kernel_arguments_NO_SHIFT_REG[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25 ;
wire \kernel_arguments_NO_SHIFT_REG[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ;
wire \kernel_arguments_NO_SHIFT_REG[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1 ;
wire \kernel_arguments_NO_SHIFT_REG[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61 ;
wire \kernel_arguments_NO_SHIFT_REG[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65 ;
wire \kernel_arguments_NO_SHIFT_REG[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53 ;
wire \kernel_arguments_NO_SHIFT_REG[152]~8 ;
wire \kernel_arguments_NO_SHIFT_REG[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57 ;
wire \kernel_arguments_NO_SHIFT_REG[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45 ;
wire \kernel_arguments_NO_SHIFT_REG[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49 ;
wire \kernel_arguments_NO_SHIFT_REG[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77 ;
wire \kernel_arguments_NO_SHIFT_REG[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81 ;
wire \kernel_arguments_NO_SHIFT_REG[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69 ;
wire \kernel_arguments_NO_SHIFT_REG[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25 ;
wire \~GND ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25] ;
wire \acl_id_iterator:id_iter_inst0|global_id[0][25]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ;
wire \kernel_arguments_NO_SHIFT_REG[91]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[88]~5 ;
wire \kernel_arguments_NO_SHIFT_REG[91] ;
wire \kernel_arguments_NO_SHIFT_REG[90] ;
wire \kernel_arguments_NO_SHIFT_REG[89] ;
wire \kernel_arguments_NO_SHIFT_REG[88] ;
wire \kernel_arguments_NO_SHIFT_REG[87]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[80]~3 ;
wire \kernel_arguments_NO_SHIFT_REG[87] ;
wire \kernel_arguments_NO_SHIFT_REG[86] ;
wire \kernel_arguments_NO_SHIFT_REG[85]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[85] ;
wire \kernel_arguments_NO_SHIFT_REG[84]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[84] ;
wire \kernel_arguments_NO_SHIFT_REG[83] ;
wire \kernel_arguments_NO_SHIFT_REG[82]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[82] ;
wire \kernel_arguments_NO_SHIFT_REG[81] ;
wire \kernel_arguments_NO_SHIFT_REG[80]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[80] ;
wire \kernel_arguments_NO_SHIFT_REG[79]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[74]~4 ;
wire \kernel_arguments_NO_SHIFT_REG[79] ;
wire \kernel_arguments_NO_SHIFT_REG[78]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[78] ;
wire \kernel_arguments_NO_SHIFT_REG[77] ;
wire \kernel_arguments_NO_SHIFT_REG[76]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[76] ;
wire \kernel_arguments_NO_SHIFT_REG[75]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[75] ;
wire \kernel_arguments_NO_SHIFT_REG[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ;
wire \kernel_arguments_NO_SHIFT_REG[92]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ;
wire \kernel_arguments_NO_SHIFT_REG[94]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[94] ;
wire \kernel_arguments_NO_SHIFT_REG[93]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \avm_local_bb1_ld__u0_inst0_waitrequest~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ;
wire \avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE ;
wire \kernel_arguments_NO_SHIFT_REG[26]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[24]~2 ;
wire \kernel_arguments_NO_SHIFT_REG[26] ;
wire \kernel_arguments_NO_SHIFT_REG[25]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[25] ;
wire \kernel_arguments_NO_SHIFT_REG[24]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[24] ;
wire \kernel_arguments_NO_SHIFT_REG[23]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[16]~0 ;
wire \kernel_arguments_NO_SHIFT_REG[23] ;
wire \kernel_arguments_NO_SHIFT_REG[22] ;
wire \kernel_arguments_NO_SHIFT_REG[21]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[21] ;
wire \kernel_arguments_NO_SHIFT_REG[20]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[20] ;
wire \kernel_arguments_NO_SHIFT_REG[19] ;
wire \kernel_arguments_NO_SHIFT_REG[18]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[18] ;
wire \kernel_arguments_NO_SHIFT_REG[17] ;
wire \kernel_arguments_NO_SHIFT_REG[16]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[16] ;
wire \kernel_arguments_NO_SHIFT_REG[15]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[10]~1 ;
wire \kernel_arguments_NO_SHIFT_REG[15] ;
wire \kernel_arguments_NO_SHIFT_REG[14]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[14] ;
wire \kernel_arguments_NO_SHIFT_REG[13] ;
wire \kernel_arguments_NO_SHIFT_REG[12]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[12] ;
wire \kernel_arguments_NO_SHIFT_REG[11]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[11] ;
wire \kernel_arguments_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ;
wire \kernel_arguments_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ;
wire \kernel_arguments_NO_SHIFT_REG[30]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[30] ;
wire \kernel_arguments_NO_SHIFT_REG[29] ;
wire \kernel_arguments_NO_SHIFT_REG[28]~feeder ;
wire \kernel_arguments_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ;
wire \avm_local_bb1_ld__inst0_waitrequest~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ;
wire \avm_local_bb1_ld__inst0_readdatavalid~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active ;
wire \float_add_function:float_add_function_inst0|has_a_lsu_active~feeder ;
wire \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted ;
wire \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2] ;
wire \workgroup_size_NO_SHIFT_REG[24]~3 ;
wire \workgroup_size_NO_SHIFT_REG[31] ;
wire \workgroup_size_NO_SHIFT_REG[30]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[30] ;
wire \workgroup_size_NO_SHIFT_REG[29]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[29] ;
wire \workgroup_size_NO_SHIFT_REG[28]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[28] ;
wire \workgroup_size_NO_SHIFT_REG[27]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[27] ;
wire \workgroup_size_NO_SHIFT_REG[26] ;
wire \workgroup_size_NO_SHIFT_REG[25]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[25] ;
wire \workgroup_size_NO_SHIFT_REG[24] ;
wire \workgroup_size_NO_SHIFT_REG[16]~2 ;
wire \workgroup_size_NO_SHIFT_REG[23] ;
wire \workgroup_size_NO_SHIFT_REG[22]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[22] ;
wire \workgroup_size_NO_SHIFT_REG[21] ;
wire \workgroup_size_NO_SHIFT_REG[20]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[20] ;
wire \workgroup_size_NO_SHIFT_REG[19] ;
wire \workgroup_size_NO_SHIFT_REG[18]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[18] ;
wire \workgroup_size_NO_SHIFT_REG[17]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[17] ;
wire \workgroup_size_NO_SHIFT_REG[16] ;
wire \workgroup_size_NO_SHIFT_REG[15]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[8]~1 ;
wire \workgroup_size_NO_SHIFT_REG[15] ;
wire \workgroup_size_NO_SHIFT_REG[14] ;
wire \workgroup_size_NO_SHIFT_REG[13]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[13] ;
wire \workgroup_size_NO_SHIFT_REG[12]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[12] ;
wire \workgroup_size_NO_SHIFT_REG[11] ;
wire \workgroup_size_NO_SHIFT_REG[10]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[10] ;
wire \workgroup_size_NO_SHIFT_REG[9] ;
wire \workgroup_size_NO_SHIFT_REG[8]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[8] ;
wire \workgroup_size_NO_SHIFT_REG[7]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[0]~0 ;
wire \workgroup_size_NO_SHIFT_REG[7] ;
wire \workgroup_size_NO_SHIFT_REG[6] ;
wire \workgroup_size_NO_SHIFT_REG[5]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[5] ;
wire \workgroup_size_NO_SHIFT_REG[4]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[4] ;
wire \workgroup_size_NO_SHIFT_REG[3]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[3] ;
wire \workgroup_size_NO_SHIFT_REG[2]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[2] ;
wire \workgroup_size_NO_SHIFT_REG[1]~feeder ;
wire \workgroup_size_NO_SHIFT_REG[1] ;
wire \workgroup_size_NO_SHIFT_REG[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~6 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~10 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~14 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~18 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~22 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~26 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~30 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~230 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~234 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~238 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~242 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~246 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~226 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~250 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~254 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~262 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~266 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~270 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~274 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~278 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~258 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~282 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~286 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~294 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~298 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~302 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~306 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~310 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~290 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~314 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~318 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~326 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~330 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~334 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~338 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~342 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~322 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~346 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~350 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~358 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~362 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~366 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~370 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~374 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~354 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~378 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~382 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~38 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~42 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~46 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~50 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~54 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG ;
wire \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder ;
wire \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~6 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~10 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~14 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~18 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~22 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~26 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~30 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~230 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~234 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~238 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~242 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~246 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~226 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~250 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~254 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~262 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~266 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~270 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~274 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~278 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~258 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~282 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~286 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~294 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~298 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~302 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~306 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~310 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~290 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~314 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~318 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~326 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~330 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~334 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~338 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~342 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~322 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~346 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~350 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~358 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~362 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~366 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~370 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~374 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~354 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~378 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~382 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~38 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~42 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~46 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~50 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~54 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~34 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~34 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~58 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~58 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal6~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal5~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal2~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal4~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal1~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal3~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal0~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~62 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~70 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~74 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~78 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~82 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~86 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~62 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~70 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~74 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~78 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~82 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~86 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~66 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~90 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~66 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~90 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal7~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~94 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~102 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~106 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~110 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~114 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~94 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~102 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~106 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~110 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~114 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~118 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~98 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~122 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~118 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~98 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~122 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal8~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~126 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~134 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~138 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~142 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~146 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~150 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~126 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~134 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~138 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~130 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~142 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~146 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~150 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~130 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~154 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~154 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal9~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~158 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~166 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~170 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~174 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~178 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~182 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~162 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~186 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~190 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~198 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~202 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~206 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~210 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~214 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~158 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~166 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~170 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~174 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~178 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~182 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~162 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~186 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~190 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~198 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~202 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~206 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~210 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~214 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~194 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~218 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~194 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~218 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal11~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|Equal10~3 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg ;
wire \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done ;
wire \acl_kernel_finish_detector:kernel_finish_detector|finish~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|finish ;
wire \started_NO_SHIFT_REG~0 ;
wire started_NO_SHIFT_REG;
wire \start_NO_SHIFT_REG~0 ;
wire start_NO_SHIFT_REG;
wire \status_NO_SHIFT_REG[3]~1 ;
wire \status_NO_SHIFT_REG[0]~3 ;
wire \status_NO_SHIFT_REG[0] ;
wire \Selector31~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[0] ;
wire \cra_addr_st1_NO_SHIFT_REG[1] ;
wire \cra_addr_st1_NO_SHIFT_REG[0] ;
wire \cra_addr_st1_NO_SHIFT_REG[2] ;
wire \cra_addr_st1_NO_SHIFT_REG[3] ;
wire \Equal0~0 ;
wire \avs_cra_readdata[0]~reg0 ;
wire \status_NO_SHIFT_REG[1]~2 ;
wire \status_NO_SHIFT_REG[1] ;
wire \Selector30~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[1] ;
wire \avs_cra_readdata[1]~reg0 ;
wire \status_NO_SHIFT_REG[3]~0 ;
wire \status_NO_SHIFT_REG[2] ;
wire \Selector29~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[2] ;
wire \avs_cra_readdata[2]~reg0 ;
wire \status_NO_SHIFT_REG[3] ;
wire \Selector28~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[3] ;
wire \avs_cra_readdata[3]~reg0 ;
wire \status_NO_SHIFT_REG[4]~feeder ;
wire \status_NO_SHIFT_REG[4] ;
wire \Selector27~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[4] ;
wire \avs_cra_readdata[4]~reg0 ;
wire \status_NO_SHIFT_REG[5] ;
wire \Selector26~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[5] ;
wire \avs_cra_readdata[5]~reg0 ;
wire \status_NO_SHIFT_REG[6]~feeder ;
wire \status_NO_SHIFT_REG[6] ;
wire \Selector25~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[6] ;
wire \avs_cra_readdata[6]~reg0 ;
wire \status_NO_SHIFT_REG[7] ;
wire \Selector24~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[7] ;
wire \avs_cra_readdata[7]~reg0 ;
wire \status_NO_SHIFT_REG[8]~4 ;
wire \status_NO_SHIFT_REG[8] ;
wire \Selector23~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[8] ;
wire \avs_cra_readdata[8]~reg0 ;
wire \status_NO_SHIFT_REG[9]~feeder ;
wire \status_NO_SHIFT_REG[9] ;
wire \Selector22~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[9] ;
wire \avs_cra_readdata[9]~reg0 ;
wire \status_NO_SHIFT_REG[10]~feeder ;
wire \status_NO_SHIFT_REG[10] ;
wire \Selector21~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[10] ;
wire \avs_cra_readdata[10]~reg0 ;
wire \float_add_function:float_add_function_inst0|has_a_lsu_active ;
wire \status_NO_SHIFT_REG[13] ;
wire \Selector19~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[12] ;
wire \avs_cra_readdata~0 ;
wire \avs_cra_readdata[12]~reg0feeder ;
wire \avs_cra_readdata[12]~reg0 ;
wire \avs_cra_readdata[13]~reg0 ;
wire \status_NO_SHIFT_REG[14] ;
wire \Selector17~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[14] ;
wire \avs_cra_readdata[14]~reg0 ;
wire \status_NO_SHIFT_REG[15] ;
wire \Selector16~0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[15] ;
wire \avs_cra_readdata[15]~reg0feeder ;
wire \avs_cra_readdata[15]~reg0 ;
wire \cra_readdata_st1_NO_SHIFT_REG[16] ;
wire \avs_cra_readdata~1 ;
wire \avs_cra_readdata[16]~reg0 ;
wire \avs_cra_readdata[17]~reg0 ;
wire \avs_cra_read~input0 ;
wire \cra_read_st1_NO_SHIFT_REG~feeder ;
wire cra_read_st1_NO_SHIFT_REG;
wire \avs_cra_readdatavalid~reg0feeder ;
wire \avs_cra_readdatavalid~reg0 ;
wire \cra_irq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[14]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[15]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[29]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[30]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[31]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[46]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[47]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[61]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[62]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[63]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[78]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[79]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[93]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[94]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[95]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[110]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[111]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[125]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[126]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[127]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[142]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[143]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[157]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[158]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[159]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[174]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[175]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[189]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[190]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[191]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[206]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[207]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[221]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[222]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[223]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[238]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[239]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[253]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[254]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[255]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ;
wire \avm_local_bb1_ld__inst0_readdata[14]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ;
wire \avm_local_bb1_ld__inst0_readdata[15]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[29]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[30]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[31]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[46]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[47]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[61]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[62]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[63]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[78]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[79]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[93]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[94]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[95]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[110]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[111]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[125]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[126]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[127]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[142]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[143]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[157]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[158]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[159]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[174]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[175]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[189]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[190]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[191]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[206]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[207]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[221]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[222]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[223]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[238]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[239]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[253]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[254]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[255]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ;
wire \avm_local_bb1_ld__u0_inst0_readdata[16]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[18]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[21]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[22]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[23]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[48]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[50]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[53]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[54]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[55]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[80]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[82]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[85]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[86]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[87]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[112]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[114]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[117]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[118]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[119]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[144]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[146]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[149]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[150]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[151]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[176]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[178]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[181]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[182]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[183]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[208]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[210]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[213]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[214]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[215]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[240]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[242]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[245]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[246]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[247]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ;
wire \avm_local_bb1_ld__inst0_readdata[16]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[18]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[21]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[22]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[23]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[48]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[50]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[53]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[54]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[55]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[80]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[82]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[85]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[86]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[87]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[112]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[114]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[117]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[118]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[119]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[144]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[146]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[149]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[150]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[151]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[176]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[178]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[181]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[182]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[183]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[208]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[210]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[213]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[214]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[215]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[240]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[242]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[245]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[246]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[247]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0 ;
wire \avm_local_bb1_ld__inst0_readdata[10]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[11]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[12]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[13]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[24]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[42]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[43]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[44]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[45]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[56]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[74]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[75]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[76]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[77]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[88]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[106]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[107]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[108]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[109]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[120]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[138]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[139]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[140]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[141]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[152]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[170]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[171]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[172]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[173]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[184]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[202]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[203]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[204]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[205]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[216]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[234]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[235]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[236]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[237]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[248]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ;
wire \avm_local_bb1_ld__u0_inst0_readdata[10]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[11]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[12]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[13]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[24]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[42]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[43]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[44]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[45]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[56]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[74]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[75]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[76]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[77]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[88]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[106]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[107]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[108]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[109]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[120]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[138]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[139]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[140]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[141]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[152]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[170]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[171]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[172]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[173]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[184]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[202]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[203]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[204]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[205]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[216]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[234]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[235]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[236]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[237]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[248]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ;
wire \avm_local_bb1_ld__inst0_readdata[17]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[19]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[20]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[25]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[26]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[49]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[51]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[52]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[57]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[58]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[81]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[83]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[84]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[89]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[90]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[113]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[115]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[116]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[121]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[122]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[145]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[147]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[148]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[153]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[154]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[177]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[179]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[180]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[185]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[186]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[209]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[211]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[212]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[217]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[218]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[241]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[243]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[244]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[249]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[250]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ;
wire \avm_local_bb1_ld__u0_inst0_readdata[17]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[19]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[20]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[25]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[26]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[49]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[51]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[52]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[57]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[58]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[81]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[83]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[84]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[89]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[90]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[113]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[115]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[116]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[121]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[122]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[145]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[147]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[148]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[153]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[154]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[177]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[179]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[180]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[185]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[186]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[209]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[211]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[212]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[217]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[218]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[241]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[243]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[244]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[249]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[250]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ;
wire \avm_local_bb1_ld__u0_inst0_readdata[5]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[6]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[7]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[8]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[9]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[37]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[38]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[39]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[40]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[41]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[69]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[70]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[71]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[72]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[73]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[101]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[102]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[103]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[104]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[105]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[133]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[134]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[135]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[136]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[137]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[165]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[166]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[167]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[168]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[169]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[197]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[198]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[199]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[200]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[201]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[229]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[230]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[231]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[232]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[233]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4 ;
wire \avm_local_bb1_ld__inst0_readdata[5]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[6]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[7]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[8]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[9]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[37]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[38]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[39]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[40]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[41]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[69]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[70]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[71]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[72]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[73]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[101]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[102]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[103]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[104]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[105]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[133]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[134]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[135]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[136]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[137]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[165]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[166]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[167]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[168]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[169]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[197]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[198]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[199]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[200]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[201]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[229]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[230]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[231]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[232]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[233]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ;
wire \avm_local_bb1_ld__u0_inst0_readdata[0]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[1]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[2]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[3]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[4]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[32]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[33]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[34]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[35]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[36]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[64]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[65]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[66]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[67]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[68]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[96]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[97]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[98]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[99]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[100]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[128]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[129]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[130]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[131]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[132]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[160]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[161]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[162]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[163]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[164]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[192]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[193]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[194]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[195]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[196]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[224]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[225]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[226]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[227]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[228]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ;
wire \avm_local_bb1_ld__inst0_readdata[0]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[1]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[2]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[3]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[4]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[32]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[33]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[34]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[35]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[36]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[64]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[65]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[66]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[67]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[68]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[96]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[97]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[98]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[99]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[100]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[128]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[129]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[130]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[131]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[132]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[160]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[161]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[162]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[163]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[164]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[192]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[193]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[194]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[195]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[196]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[224]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[225]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[226]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[227]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[228]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[27]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[28]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[59]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[60]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[91]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[92]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[123]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[124]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[155]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[156]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[187]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[188]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[219]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[220]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[251]~input0 ;
wire \avm_local_bb1_ld__u0_inst0_readdata[252]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ;
wire \avm_local_bb1_ld__inst0_readdata[27]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[28]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[59]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[60]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[91]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[92]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[123]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[124]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[155]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[156]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[187]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[188]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[219]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[220]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[251]~input0 ;
wire \avm_local_bb1_ld__inst0_readdata[252]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~106 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~98 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~110 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~102 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~98 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~102 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~106 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~110 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~114 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~118 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~122 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[192]~160 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][193]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[193]~161 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[194]~162 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[195]~163 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][196]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[196]~164 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[197]~165 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][198]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[198]~166 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[199]~167 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[200]~168 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[201]~169 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[202]~170 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][203]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[203]~171 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[204]~172 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][205]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[205]~173 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][206]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[206]~174 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][207]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[207]~175 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][208]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[208]~176 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][209]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[209]~177 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[210]~178 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[211]~179 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][212]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[212]~180 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][213]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][213]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[213]~181 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][214]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[214]~182 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][215]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[215]~183 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][216]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[216]~184 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[217]~185 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][218]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[218]~186 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[219]~187 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][220]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[220]~188 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[221]~189 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][222]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[222]~190 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][223]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[223]~191 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][224]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[224]~192 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][225]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[225]~193 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[226]~194 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][227]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[227]~195 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[228]~196 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][229]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[229]~197 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[230]~198 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][231]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[231]~199 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[247]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[247]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[225]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[226]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[228]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[229]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[231]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[232]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[233]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[234]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[236]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[237]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[239]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][232]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[232]~200 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][233]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[233]~201 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[234]~202 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[235]~203 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][236]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[236]~204 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][237]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[237]~205 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][238]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[238]~206 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][239]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[239]~207 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[240]~208 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[241]~209 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[242]~210 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][243]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[243]~211 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][244]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[244]~212 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][245]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[245]~213 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][246]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[246]~214 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][247]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[247]~215 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][248]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[248]~216 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][249]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[249]~217 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][250]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[250]~218 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][251]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[251]~219 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][252]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[252]~220 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][253]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[253]~221 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][254]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[254]~222 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[255]~223 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[256] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][256] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[256] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[256]~224 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][257]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[257]~225 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][258]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[258]~226 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[259] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][259] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[259] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[259]~227 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[260] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][260] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[260] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[260]~228 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][261]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[261]~229 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][262]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[262]~230 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][263]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[263]~231 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[264] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][264] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[264] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[264]~232 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[265] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][265] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[265] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[265]~233 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][266]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[266]~234 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][267]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[267]~235 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][268]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[268]~236 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][269]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[269]~237 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][270]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[270]~238 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][271]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[271]~239 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[240]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[241]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[242]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[244]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[246]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[247]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[248]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[253]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[254]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[255]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][272]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[272]~240 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[273] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][273] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[273] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[273]~241 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][274]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[274]~242 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[275] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][275] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[275] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[275]~243 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[276] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][276] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[276] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[276]~244 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[277] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][277] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[277] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[277]~245 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][278]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[278]~246 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][279]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[279]~247 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][280]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[280]~248 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][281]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[281]~249 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][282]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[282]~250 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][283]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[283]~251 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][284]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[284]~252 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[285] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][285] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[285] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[285]~253 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][286]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[286]~254 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][287]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[287]~255 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~256 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~257 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~258 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~259 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~260 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~261 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~262 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~263 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~264 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~265 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~266 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~267 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~268 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~269 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~270 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~271 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~272 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~273 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~274 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~275 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~276 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~277 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~278 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~279 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~280 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~281 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~282 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~283 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~284 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~285 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~286 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[31]~287 ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit ;
wire [191:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit ;
wire [0:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [5:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next ;
wire [0:0] \acl_work_group_dispatcher:group_dispatcher|valid_out ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr ;
wire [30:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst ;
wire [0:0] \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr ;
wire [0:0] \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0 ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [2:0] \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2 ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr ;
wire [63:0] cra_readdata_st1_NO_SHIFT_REG;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data ;
wire [296:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1 ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b ;
wire [31:0] status_NO_SHIFT_REG;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS ;
wire [255:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable ;
wire [30:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt ;
wire [255:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst ;
wire [30:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya ;
wire [95:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit ;
wire [30:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold ;
wire [296:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2 ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0 ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr ;
wire [31:0] \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1 ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [1:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit ;
wire [8:0] \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG ;
wire [191:0] kernel_arguments_NO_SHIFT_REG;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter ;
wire [30:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG ;
wire [31:0] workgroup_size_NO_SHIFT_REG;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [2:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter ;
wire [12:0] \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya ;
wire [0:0] \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa ;
wire [25:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1 ;
wire [3:0] cra_addr_st1_NO_SHIFT_REG;
wire [6:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in ;
wire [5:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit ;
wire [3:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit ;
wire [255:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit ;
wire [8:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit ;
wire [7:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG ;
wire [63:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit ;
wire [1:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [5:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr ;
wire [0:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS ;
wire [4:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;
wire [1:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy ;
wire [31:0] \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG ;

wire \__ALT_INV__avs_cra_writedata[55]~input0 ;
wire \__ALT_INV__avs_cra_writedata[54]~input0 ;
wire \__ALT_INV__avs_cra_writedata[53]~input0 ;
wire \__ALT_INV__avs_cra_writedata[52]~input0 ;
wire \__ALT_INV__avs_cra_writedata[51]~input0 ;
wire \__ALT_INV__avs_cra_writedata[50]~input0 ;
wire \__ALT_INV__avs_cra_writedata[58]~input0 ;
wire \__ALT_INV__avs_cra_writedata[57]~input0 ;
wire \__ALT_INV__avs_cra_writedata[56]~input0 ;
wire \__ALT_INV__avs_cra_writedata[61]~input0 ;
wire \__ALT_INV__avs_cra_writedata[60]~input0 ;
wire \__ALT_INV__avs_cra_writedata[59]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[7]~input0 ;
wire \__ALT_INV__avs_cra_writedata[62]~input0 ;
wire \__ALT_INV__avs_cra_writedata[37]~input0 ;
wire \__ALT_INV__avs_cra_writedata[36]~input0 ;
wire \__ALT_INV__avs_cra_writedata[35]~input0 ;
wire \__ALT_INV__avs_cra_writedata[34]~input0 ;
wire \__ALT_INV__avs_cra_writedata[33]~input0 ;
wire \__ALT_INV__avs_cra_writedata[40]~input0 ;
wire \__ALT_INV__avs_cra_writedata[39]~input0 ;
wire \__ALT_INV__avs_cra_writedata[43]~input0 ;
wire \__ALT_INV__avs_cra_writedata[42]~input0 ;
wire \__ALT_INV__avs_cra_writedata[46]~input0 ;
wire \__ALT_INV__avs_cra_writedata[45]~input0 ;
wire \__ALT_INV__avs_cra_writedata[44]~input0 ;
wire \__ALT_INV__avs_cra_writedata[49]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[6]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[5]~input0 ;
wire \__ALT_INV__avs_cra_writedata[47]~input0 ;
wire \__ALT_INV__avs_cra_writedata[31]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[4]~input0 ;
wire \__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ;
wire \__ALT_INV__avs_cra_writedata[27]~input0 ;
wire \__ALT_INV__avs_cra_writedata[26]~input0 ;
wire \__ALT_INV__avs_cra_writedata[25]~input0 ;
wire \__ALT_INV__avs_cra_writedata[24]~input0 ;
wire \__ALT_INV__avs_cra_writedata[23]~input0 ;
wire \__ALT_INV__avs_cra_writedata[30]~input0 ;
wire \__ALT_INV__avs_cra_writedata[29]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[3]~input0 ;
wire \__ALT_INV__avs_cra_writedata[28]~input0 ;
wire \__ALT_INV__avs_cra_writedata[12]~input0 ;
wire \__ALT_INV__avs_cra_writedata[11]~input0 ;
wire \__ALT_INV__avs_cra_writedata[16]~input0 ;
wire \__ALT_INV__avs_cra_writedata[15]~input0 ;
wire \__ALT_INV__avs_cra_writedata[14]~input0 ;
wire \__ALT_INV__avs_cra_writedata[19]~input0 ;
wire \__ALT_INV__avs_cra_writedata[18]~input0 ;
wire \__ALT_INV__avs_cra_writedata[22]~input0 ;
wire \__ALT_INV__avs_cra_writedata[21]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[2]~input0 ;
wire \__ALT_INV__avs_cra_writedata[20]~input0 ;
wire \__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ;
wire \__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ;
wire \__ALT_INV__avs_cra_writedata[10]~input0 ;
wire \__ALT_INV__avs_cra_writedata[9]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[1]~input0 ;
wire \__ALT_INV__avs_cra_writedata[8]~input0 ;
wire \__ALT_INV__avs_cra_writedata[7]~input0 ;
wire \__ALT_INV__avs_cra_writedata[6]~input0 ;
wire \__ALT_INV__avs_cra_writedata[5]~input0 ;
wire \__ALT_INV__avs_cra_writedata[4]~input0 ;
wire \__ALT_INV__avs_cra_writedata[2]~input0 ;
wire \__ALT_INV__avs_cra_writedata[0]~input0 ;
wire \__ALT_INV__avs_cra_read~input0 ;
wire \__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0 ;
wire \__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ;
wire \__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ;
wire \__ALT_INV__avs_cra_writedata[1]~input0 ;
wire \__ALT_INV__avs_cra_address[2]~input0 ;
wire \__ALT_INV__avs_cra_address[1]~input0 ;
wire \__ALT_INV__avs_cra_address[0]~input0 ;
wire \__ALT_INV__avs_cra_write~input0 ;
wire \__ALT_INV__avs_cra_address[3]~input0 ;
wire \__ALT_INV__avs_cra_byteenable[0]~input0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][4] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][3] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][2] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][1] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][8] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][7] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][6] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][11] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][10] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][9] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][14] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][13] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][12] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][17] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][16] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][15] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][0] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][0] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__shift_reg ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__stall_in ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_combined_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__combined_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__valid_out_0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__accept_inc_bin[0] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__LessThan1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_var__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_var__output_regs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~2 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[8] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~1 ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~0 ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_stalled_by_successors ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~8 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~7 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~4 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~3 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~2 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~1 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~0 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1 ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[91] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[90] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[89] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[88] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[87] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[94] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[93] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[92] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[74] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[77] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[76] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[75] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[80] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[79] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[78] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[83] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[82] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[81] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[86] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[85] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1 ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[25] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[24] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[23] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[22] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[27] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[26] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[10] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[9] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[14] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[13] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[12] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[17] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[16] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[15] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[20] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[19] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_stall_in_0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[1] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[2] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[3] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[5] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[6] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[7] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[8] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__always1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~0 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_active ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~12 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~11 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~10 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~8 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~7 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~6 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~4 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~3 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~2 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~0 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[15] ;
wire \acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__delayed_start ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[247]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[208]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[176]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[159]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~95 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~92 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~86 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~83 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~80 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~77 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~74 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~68 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~65 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~62 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~56 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~50 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~47 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~38 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[28]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[27]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[30]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[29]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[22]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[21]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[24]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[23]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[26]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[25]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[17]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[16]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[15]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[19]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[18]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[10]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[9]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[12]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[11]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[14]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[13]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[20]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__always1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_inputs_ready~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~7 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[3]~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~14 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~15 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or130_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~6 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[0]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~6 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~10 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~12 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~11 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal11~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal8~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[3]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[5]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[4]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[15]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[6]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[21]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[13]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[23]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[15]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[7]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[22]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[14]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[20]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[12]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal6~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~32 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~31 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[19]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[8]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[23]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[9]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[12]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[3]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[5]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[4]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[6]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[7]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[16]~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[6]~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[9]~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[8]~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[4]~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[5]~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal20~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[1]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[0]~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[2]~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[1]~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[14]~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[15]~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[18]~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[17]~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[19]~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[7]~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[10]~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[11]~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[12]~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[13]~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[3]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or263_i[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__31_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal21~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_11_i ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__SFC_1_VALID_165_166_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[31] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[30] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[28] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[27] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[26] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[25] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[24] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[29] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[23] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[22] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[20] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[19] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[18] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[17] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[16] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[21] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[15] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[14] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[12] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[11] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[10] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[9] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[8] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[13] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[7] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[6] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[4] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[3] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[2] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[1] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__completed_items_incr[0] ;
wire \__ALT_INV__workgroup_size_NO_SHIFT_REG[5] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][22] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][21] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][19] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][18] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][23] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][20] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][25] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][24] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][26] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][28] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][27] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][31] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][30] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][29] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][4] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][3] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][1] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][5] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][2] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][7] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][6] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][8] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][10] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][9] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][11] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][13] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][12] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][14] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][16] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][15] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[2][17] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][22] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][21] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][19] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][18] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][23] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][20] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][25] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][24] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][26] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][28] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][27] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][31] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][30] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][29] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][4] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][3] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][1] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][5] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][2] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][7] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][6] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][8] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][10] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][9] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][11] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][13] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][12] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][14] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][16] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][15] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[1][17] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][22] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][21] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][19] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][18] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][23] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][20] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][25] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][24] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][26] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][28] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][27] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][31] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][30] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][29] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][4] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][3] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][1] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][5] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][2] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][7] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][6] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][8] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][10] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][9] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][11] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][13] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][12] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][14] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][16] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][15] ;
wire \__ALT_INV__num_groups_NO_SHIFT_REG[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[6] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[156] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[155] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[158] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[157] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[150] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[149] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[152] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[151] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[154] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[153] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[145] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[144] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[143] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[147] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[146] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[138] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[140] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[139] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[142] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[141] ;
wire \__ALT_INV__kernel_arguments_NO_SHIFT_REG[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[4] ;
wire \acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][23] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][22] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][21] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][20] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][19] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][18] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][26] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][25] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][24] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][29] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][28] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][27] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][31] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][30] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][5] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][4] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][3] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][2] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][1] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][8] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][7] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][6] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][11] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][10] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][9] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][14] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][13] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][12] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][17] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][16] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[1][15] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][23] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][22] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][21] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][20] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][19] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][18] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][26] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][25] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][24] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][29] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][28] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][27] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][31] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][30] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][5] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][4] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][3] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][2] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][1] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][8] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][7] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][6] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][11] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][10] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][9] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][14] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][13] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][12] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][17] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][16] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[0][15] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][23] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][22] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][21] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][20] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][19] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][18] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][26] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][25] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][24] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][29] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][28] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][27] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][31] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][30] ;
wire \__ALT_INV__local_size_NO_SHIFT_REG[2][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|__ALT_INV__has_a_lsu_active~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][213]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][121]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][83]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][25]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][23]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][21]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][11]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][10]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][14]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][18]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][7]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][4]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5]~DUPLICATE ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6]~DUPLICATE ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17]~DUPLICATE ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_inputs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__inputs_ready ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|__ALT_INV__o_active ;
wire __ALT_INV__started_NO_SHIFT_REG;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__empty_dff ;
wire __ALT_INV__start_NO_SHIFT_REG;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Equal1~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ;
wire \__ALT_INV__status_NO_SHIFT_REG[15] ;
wire \__ALT_INV__status_NO_SHIFT_REG[14] ;
wire \__ALT_INV__status_NO_SHIFT_REG[13] ;
wire \__ALT_INV__status_NO_SHIFT_REG[10] ;
wire \__ALT_INV__status_NO_SHIFT_REG[9] ;
wire \__ALT_INV__status_NO_SHIFT_REG[8] ;
wire \__ALT_INV__status_NO_SHIFT_REG[7] ;
wire \__ALT_INV__status_NO_SHIFT_REG[6] ;
wire \__ALT_INV__status_NO_SHIFT_REG[5] ;
wire \__ALT_INV__status_NO_SHIFT_REG[4] ;
wire \__ALT_INV__status_NO_SHIFT_REG[2] ;
wire \__ALT_INV__WideOr1~0 ;
wire \__ALT_INV__status_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__write_accepted ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish ;
wire \__ALT_INV__status_NO_SHIFT_REG[3]~1 ;
wire __ALT_INV__cra_read_st1_NO_SHIFT_REG;
wire \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[16] ;
wire \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[15] ;
wire \__ALT_INV__avs_cra_readdata~0 ;
wire \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[12] ;
wire \__ALT_INV__Equal0~0 ;
wire \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[0] ;
wire \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[1] ;
wire \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[2] ;
wire \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[4]~30 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[3]~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[2]~28 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[1]~27 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[0]~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][285] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[285] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][277] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[277] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][276] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[276] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][275] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[275] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][273] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[273] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][265] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[265] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][264] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[264] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][260] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[260] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][259] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[259] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][256] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[256] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[3]~37 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[2]~33 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[1]~29 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[5]~25 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[4]~21 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[0]~1 ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][47] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][47] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][46] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][44] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][43] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][42] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][42] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][41] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][41] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][40] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][40] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][45] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][45] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][39] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][39] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][36] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][36] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][35] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][35] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][34] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][34] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][32] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][32] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][37] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][31] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][31] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][30] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][27] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][27] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][26] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][26] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][25] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][24] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][29] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][29] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][23] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][22] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][22] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][18] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][17] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][17] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][16] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][16] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][15] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][14] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][14] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][12] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][13] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][95] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][95] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][94] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][94] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][92] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][92] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][91] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][91] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][90] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][90] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][89] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][89] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][88] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][87] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][86] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][84] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][83] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][82] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][82] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][81] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][81] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][80] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][85] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][79] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][78] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][76] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][75] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][74] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][72] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][77] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][77] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][70] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][70] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][68] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][65] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][65] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][63] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][62] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][62] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][60] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][58] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][58] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][57] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][57] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][56] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][61] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][54] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][54] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][52] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][52] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][51] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][51] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][50] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][50] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][49] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][48] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][53] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][17] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][22] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][21] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][19] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][18] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][23] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][20] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][25] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][24] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][26] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][28] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][27] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][30] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][3] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][0] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][5] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][2] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][7] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][8] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][10] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][9] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][11] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][13] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][14] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][16] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[5] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[4] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[2] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[1] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[11] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[10] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[9] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[8] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[7] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[6] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[29] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[30] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[15] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__cmp_result_reg ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__pipelined_dispatched_all_groups[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~69 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~61 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~53 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~45 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~9 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][1] ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add2~29 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~113 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~113 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[4] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[5] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[6] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[7] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[8] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[9] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[10] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[11] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[12] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[13] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[14] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[15] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[16] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[17] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[18] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[19] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[20] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[21] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[22] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[23] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[24] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[25] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[26] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[27] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~109 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~109 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~105 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~105 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~101 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~97 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~97 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~93 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~89 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~89 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~85 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~85 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~81 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~81 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~77 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~77 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~73 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~69 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~65 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~61 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~61 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~57 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~53 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~53 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~49 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~49 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~45 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~45 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~41 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~41 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~37 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][4] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~17 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~13 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~9 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~37 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~33 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~29 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~25 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~21 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~17 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~13 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~9 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~5 ;
wire \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~1 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_valid~0 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ;
wire \__ALT_INV__status_NO_SHIFT_REG[1] ;
wire \__ALT_INV__status_NO_SHIFT_REG[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~26 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~33 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish_asserted ;
wire \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__ndrange_done ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[6] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[9] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[13] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[20] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[22] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[23] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[24] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[25] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[26] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[28] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[29] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[30] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[1] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[11] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[15] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[16] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[17] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[19] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[21] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[272] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[274] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[278] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[279] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[280] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[281] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[282] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[283] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[284] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[286] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[287] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[0] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[233] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[236] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[237] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[238] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[239] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[243] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[244] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[245] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[246] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[247] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[248] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[249] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[250] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[251] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[252] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[253] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[254] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[257] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[258] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[261] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[262] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[263] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[266] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[267] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[268] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[269] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[270] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[271] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[232] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[193] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[196] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[198] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[203] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[205] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[206] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[207] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[208] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[209] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[212] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[213] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[214] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[215] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[216] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[218] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[220] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[222] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[223] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[224] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[225] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[227] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[229] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[231] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[153] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[155] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[157] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[158] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[161] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[162] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[163] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[164] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[165] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[166] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[167] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[169] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[171] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[172] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[173] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[175] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[177] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[178] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[179] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[180] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[182] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[183] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[184] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[186] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[187] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[189] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[190] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[191] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[113] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[114] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[116] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[118] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[119] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[120] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[121] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[123] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[124] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[127] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[128] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[129] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[130] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[133] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[135] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[136] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[137] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[140] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[141] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[142] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[144] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[145] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[147] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[149] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[150] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[112] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[74] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[75] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[76] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[77] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[78] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[79] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[83] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[84] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[85] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[87] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[88] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[89] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[90] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[91] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[92] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[93] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[94] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[96] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[97] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[98] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[100] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[101] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[102] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[104] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[106] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[107] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[108] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[109] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[110] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[72] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[33] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[34] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[35] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[38] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[39] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[40] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[42] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[43] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[44] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[45] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[47] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[48] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[49] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[50] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[51] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[52] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[53] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[55] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[57] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[58] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[60] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[61] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[62] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[63] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[64] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[66] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[68] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[69] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[70] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[71] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[32] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~37 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~37 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~33 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~33 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~29 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~29 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~25 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~21 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~21 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~5 ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][24] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][23] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][22] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][21] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][28] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][27] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][26] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~17 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~13 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~13 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][5] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~9 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~5 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~5 ;
wire \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][3] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~1 ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][11] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][10] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][9] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][14] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][13] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][12] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][17] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][16] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][15] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][20] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][19] ;
wire \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][18] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7] ;
wire \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8] ;

wire gnd;
wire vcc;

assign gnd = 1'b0;
assign vcc = 1'b1;

assign \__ALT_INV__avs_cra_writedata[55]~input0  = ~ \avs_cra_writedata[55]~input0 ;
assign \__ALT_INV__avs_cra_writedata[54]~input0  = ~ \avs_cra_writedata[54]~input0 ;
assign \__ALT_INV__avs_cra_writedata[53]~input0  = ~ \avs_cra_writedata[53]~input0 ;
assign \__ALT_INV__avs_cra_writedata[52]~input0  = ~ \avs_cra_writedata[52]~input0 ;
assign \__ALT_INV__avs_cra_writedata[51]~input0  = ~ \avs_cra_writedata[51]~input0 ;
assign \__ALT_INV__avs_cra_writedata[50]~input0  = ~ \avs_cra_writedata[50]~input0 ;
assign \__ALT_INV__avs_cra_writedata[58]~input0  = ~ \avs_cra_writedata[58]~input0 ;
assign \__ALT_INV__avs_cra_writedata[57]~input0  = ~ \avs_cra_writedata[57]~input0 ;
assign \__ALT_INV__avs_cra_writedata[56]~input0  = ~ \avs_cra_writedata[56]~input0 ;
assign \__ALT_INV__avs_cra_writedata[61]~input0  = ~ \avs_cra_writedata[61]~input0 ;
assign \__ALT_INV__avs_cra_writedata[60]~input0  = ~ \avs_cra_writedata[60]~input0 ;
assign \__ALT_INV__avs_cra_writedata[59]~input0  = ~ \avs_cra_writedata[59]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[7]~input0  = ~ \avs_cra_byteenable[7]~input0 ;
assign \__ALT_INV__avs_cra_writedata[62]~input0  = ~ \avs_cra_writedata[62]~input0 ;
assign \__ALT_INV__avs_cra_writedata[37]~input0  = ~ \avs_cra_writedata[37]~input0 ;
assign \__ALT_INV__avs_cra_writedata[36]~input0  = ~ \avs_cra_writedata[36]~input0 ;
assign \__ALT_INV__avs_cra_writedata[35]~input0  = ~ \avs_cra_writedata[35]~input0 ;
assign \__ALT_INV__avs_cra_writedata[34]~input0  = ~ \avs_cra_writedata[34]~input0 ;
assign \__ALT_INV__avs_cra_writedata[33]~input0  = ~ \avs_cra_writedata[33]~input0 ;
assign \__ALT_INV__avs_cra_writedata[40]~input0  = ~ \avs_cra_writedata[40]~input0 ;
assign \__ALT_INV__avs_cra_writedata[39]~input0  = ~ \avs_cra_writedata[39]~input0 ;
assign \__ALT_INV__avs_cra_writedata[43]~input0  = ~ \avs_cra_writedata[43]~input0 ;
assign \__ALT_INV__avs_cra_writedata[42]~input0  = ~ \avs_cra_writedata[42]~input0 ;
assign \__ALT_INV__avs_cra_writedata[46]~input0  = ~ \avs_cra_writedata[46]~input0 ;
assign \__ALT_INV__avs_cra_writedata[45]~input0  = ~ \avs_cra_writedata[45]~input0 ;
assign \__ALT_INV__avs_cra_writedata[44]~input0  = ~ \avs_cra_writedata[44]~input0 ;
assign \__ALT_INV__avs_cra_writedata[49]~input0  = ~ \avs_cra_writedata[49]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[6]~input0  = ~ \avs_cra_byteenable[6]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[5]~input0  = ~ \avs_cra_byteenable[5]~input0 ;
assign \__ALT_INV__avs_cra_writedata[47]~input0  = ~ \avs_cra_writedata[47]~input0 ;
assign \__ALT_INV__avs_cra_writedata[31]~input0  = ~ \avs_cra_writedata[31]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[4]~input0  = ~ \avs_cra_byteenable[4]~input0 ;
assign \__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0  = ~ \avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ;
assign \__ALT_INV__avs_cra_writedata[27]~input0  = ~ \avs_cra_writedata[27]~input0 ;
assign \__ALT_INV__avs_cra_writedata[26]~input0  = ~ \avs_cra_writedata[26]~input0 ;
assign \__ALT_INV__avs_cra_writedata[25]~input0  = ~ \avs_cra_writedata[25]~input0 ;
assign \__ALT_INV__avs_cra_writedata[24]~input0  = ~ \avs_cra_writedata[24]~input0 ;
assign \__ALT_INV__avs_cra_writedata[23]~input0  = ~ \avs_cra_writedata[23]~input0 ;
assign \__ALT_INV__avs_cra_writedata[30]~input0  = ~ \avs_cra_writedata[30]~input0 ;
assign \__ALT_INV__avs_cra_writedata[29]~input0  = ~ \avs_cra_writedata[29]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[3]~input0  = ~ \avs_cra_byteenable[3]~input0 ;
assign \__ALT_INV__avs_cra_writedata[28]~input0  = ~ \avs_cra_writedata[28]~input0 ;
assign \__ALT_INV__avs_cra_writedata[12]~input0  = ~ \avs_cra_writedata[12]~input0 ;
assign \__ALT_INV__avs_cra_writedata[11]~input0  = ~ \avs_cra_writedata[11]~input0 ;
assign \__ALT_INV__avs_cra_writedata[16]~input0  = ~ \avs_cra_writedata[16]~input0 ;
assign \__ALT_INV__avs_cra_writedata[15]~input0  = ~ \avs_cra_writedata[15]~input0 ;
assign \__ALT_INV__avs_cra_writedata[14]~input0  = ~ \avs_cra_writedata[14]~input0 ;
assign \__ALT_INV__avs_cra_writedata[19]~input0  = ~ \avs_cra_writedata[19]~input0 ;
assign \__ALT_INV__avs_cra_writedata[18]~input0  = ~ \avs_cra_writedata[18]~input0 ;
assign \__ALT_INV__avs_cra_writedata[22]~input0  = ~ \avs_cra_writedata[22]~input0 ;
assign \__ALT_INV__avs_cra_writedata[21]~input0  = ~ \avs_cra_writedata[21]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[2]~input0  = ~ \avs_cra_byteenable[2]~input0 ;
assign \__ALT_INV__avs_cra_writedata[20]~input0  = ~ \avs_cra_writedata[20]~input0 ;
assign \__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0  = ~ \avm_local_bb1_ld__inst0_readdatavalid~input0 ;
assign \__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0  = ~ \avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ;
assign \__ALT_INV__avs_cra_writedata[10]~input0  = ~ \avs_cra_writedata[10]~input0 ;
assign \__ALT_INV__avs_cra_writedata[9]~input0  = ~ \avs_cra_writedata[9]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[1]~input0  = ~ \avs_cra_byteenable[1]~input0 ;
assign \__ALT_INV__avs_cra_writedata[8]~input0  = ~ \avs_cra_writedata[8]~input0 ;
assign \__ALT_INV__avs_cra_writedata[7]~input0  = ~ \avs_cra_writedata[7]~input0 ;
assign \__ALT_INV__avs_cra_writedata[6]~input0  = ~ \avs_cra_writedata[6]~input0 ;
assign \__ALT_INV__avs_cra_writedata[5]~input0  = ~ \avs_cra_writedata[5]~input0 ;
assign \__ALT_INV__avs_cra_writedata[4]~input0  = ~ \avs_cra_writedata[4]~input0 ;
assign \__ALT_INV__avs_cra_writedata[2]~input0  = ~ \avs_cra_writedata[2]~input0 ;
assign \__ALT_INV__avs_cra_writedata[0]~input0  = ~ \avs_cra_writedata[0]~input0 ;
assign \__ALT_INV__avs_cra_read~input0  = ~ \avs_cra_read~input0 ;
assign \__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0  = ~ \avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0 ;
assign \__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0  = ~ \avm_local_bb1_ld__u0_inst0_waitrequest~input0 ;
assign \__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0  = ~ \avm_local_bb1_ld__inst0_waitrequest~input0 ;
assign \__ALT_INV__avs_cra_writedata[1]~input0  = ~ \avs_cra_writedata[1]~input0 ;
assign \__ALT_INV__avs_cra_address[2]~input0  = ~ \avs_cra_address[2]~input0 ;
assign \__ALT_INV__avs_cra_address[1]~input0  = ~ \avs_cra_address[1]~input0 ;
assign \__ALT_INV__avs_cra_address[0]~input0  = ~ \avs_cra_address[0]~input0 ;
assign \__ALT_INV__avs_cra_write~input0  = ~ \avs_cra_write~input0 ;
assign \__ALT_INV__avs_cra_address[3]~input0  = ~ \avs_cra_address[3]~input0 ;
assign \__ALT_INV__avs_cra_byteenable[0]~input0  = ~ \avs_cra_byteenable[0]~input0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][4]  = ~ \local_size_NO_SHIFT_REG[2][4] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][3]  = ~ \local_size_NO_SHIFT_REG[2][3] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][2]  = ~ \local_size_NO_SHIFT_REG[2][2] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][1]  = ~ \local_size_NO_SHIFT_REG[2][1] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][8]  = ~ \local_size_NO_SHIFT_REG[2][8] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][7]  = ~ \local_size_NO_SHIFT_REG[2][7] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][6]  = ~ \local_size_NO_SHIFT_REG[2][6] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][11]  = ~ \local_size_NO_SHIFT_REG[2][11] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][10]  = ~ \local_size_NO_SHIFT_REG[2][10] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][9]  = ~ \local_size_NO_SHIFT_REG[2][9] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][14]  = ~ \local_size_NO_SHIFT_REG[2][14] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][13]  = ~ \local_size_NO_SHIFT_REG[2][13] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][12]  = ~ \local_size_NO_SHIFT_REG[2][12] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][17]  = ~ \local_size_NO_SHIFT_REG[2][17] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][16]  = ~ \local_size_NO_SHIFT_REG[2][16] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][15]  = ~ \local_size_NO_SHIFT_REG[2][15] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][0]  = ~ \num_groups_NO_SHIFT_REG[2][0] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][0]  = ~ \num_groups_NO_SHIFT_REG[1][0] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][0]  = ~ \num_groups_NO_SHIFT_REG[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_output_regs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__shift_reg  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_output_regs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__stall_in  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_combined_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__combined_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__output_regs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__valid_out_0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__accept_inc_bin[0]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__LessThan1~0  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_var__output_regs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_var__output_regs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~2  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][0]  = ~ \local_size_NO_SHIFT_REG[1][0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~8  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~7  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1 ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][0]  = ~ \local_size_NO_SHIFT_REG[0][0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~0  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0 ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][0]  = ~ \local_size_NO_SHIFT_REG[2][0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~8  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~7  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~13  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_stalled_by_successors  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~9  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~9 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~8  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~8 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~7  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~7 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~6  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~6 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~5  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~5 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~4  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~4 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~3  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~3 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~2  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~2 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~1  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~1 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~0  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~0 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~0  = ~ \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~9  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~9 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~8  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~8 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~7  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~7 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~6  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~6 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~5  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~5 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~4  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~4 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~3  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~3 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~2  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~2 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~1  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~1 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~0  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~0 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~9  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~9 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~8  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~8 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~7  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~7 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~6  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~6 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~5  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~5 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~4  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~4 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~3  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~3 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~2  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~2 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~1  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~1 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~0  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~0 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started  = ~ \acl_work_group_dispatcher:group_dispatcher|started ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[91]  = ~ \kernel_arguments_NO_SHIFT_REG[91] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[90]  = ~ \kernel_arguments_NO_SHIFT_REG[90] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[89]  = ~ \kernel_arguments_NO_SHIFT_REG[89] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[88]  = ~ \kernel_arguments_NO_SHIFT_REG[88] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[87]  = ~ \kernel_arguments_NO_SHIFT_REG[87] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[94]  = ~ \kernel_arguments_NO_SHIFT_REG[94] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[93]  = ~ \kernel_arguments_NO_SHIFT_REG[93] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[92]  = ~ \kernel_arguments_NO_SHIFT_REG[92] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[74]  = ~ \kernel_arguments_NO_SHIFT_REG[74] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[77]  = ~ \kernel_arguments_NO_SHIFT_REG[77] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[76]  = ~ \kernel_arguments_NO_SHIFT_REG[76] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[75]  = ~ \kernel_arguments_NO_SHIFT_REG[75] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[80]  = ~ \kernel_arguments_NO_SHIFT_REG[80] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[79]  = ~ \kernel_arguments_NO_SHIFT_REG[79] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[78]  = ~ \kernel_arguments_NO_SHIFT_REG[78] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[83]  = ~ \kernel_arguments_NO_SHIFT_REG[83] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[82]  = ~ \kernel_arguments_NO_SHIFT_REG[82] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[81]  = ~ \kernel_arguments_NO_SHIFT_REG[81] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[86]  = ~ \kernel_arguments_NO_SHIFT_REG[86] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[85]  = ~ \kernel_arguments_NO_SHIFT_REG[85] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[84]  = ~ \kernel_arguments_NO_SHIFT_REG[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[27]  = ~ \kernel_arguments_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[26]  = ~ \kernel_arguments_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[25]  = ~ \kernel_arguments_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[24]  = ~ \kernel_arguments_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[23]  = ~ \kernel_arguments_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[30]  = ~ \kernel_arguments_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[29]  = ~ \kernel_arguments_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[28]  = ~ \kernel_arguments_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[10]  = ~ \kernel_arguments_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[13]  = ~ \kernel_arguments_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[12]  = ~ \kernel_arguments_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[11]  = ~ \kernel_arguments_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[16]  = ~ \kernel_arguments_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[15]  = ~ \kernel_arguments_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[14]  = ~ \kernel_arguments_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[19]  = ~ \kernel_arguments_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[18]  = ~ \kernel_arguments_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[17]  = ~ \kernel_arguments_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[22]  = ~ \kernel_arguments_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[21]  = ~ \kernel_arguments_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[20]  = ~ \kernel_arguments_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_stall_in_0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[1]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[2]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[3]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[5]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[6]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[7]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[8]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[0]  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__always1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~1  = ~ \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~0  = ~ \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[12]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_active  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~1  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~0  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~12  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~11  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~10  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~8  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~7  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~0  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~12  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~11  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~10  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~8  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~7  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~0  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~12  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~11  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~10  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~8  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~7  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~4  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~3  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~2  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~0  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15] ;
assign \acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0  = ~ \acl_id_iterator:id_iter_inst0|issue~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0]  = ~ \acl_work_group_dispatcher:group_dispatcher|valid_out[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__delayed_start  = ~ \acl_work_group_dispatcher:group_dispatcher|delayed_start ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[247]~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[247]~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[208]~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[176]~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[159]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~95  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~94  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~92  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~88  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~86  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~85  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~84  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~83  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~82  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~81  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~80  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~78  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~77  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~76  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~75  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~74  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~72  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~68  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~67  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~65  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~64  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~63  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~62  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~61  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~60  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~58  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~57  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~56  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~52  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~50  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~49  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~48  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~47  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~46  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~42  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~40  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~39  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~38  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~37  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~36  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~34  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~33  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~30  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~28  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~26  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[28]~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[27]~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[30]~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[29]~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[22]~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[21]~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[24]~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[23]~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[26]~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[25]~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[17]~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[16]~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[15]~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[19]~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[18]~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[10]~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[9]~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[12]~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[11]~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[14]~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[13]~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[20]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__always1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_inputs_ready~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__o_stall  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add3~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[3]~11  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~15  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~15 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~14  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~14 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~15  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~15 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~14  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~14 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~15  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~15 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~14  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or130_i[0]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[0]~10  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~6  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~13  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~13 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~12  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~12 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~11  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~11 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~10  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal0~10 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~13  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~13 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~12  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~12 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~11  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~11 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~10  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal1~10 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~13  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~13 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~12  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~12 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~11  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~11 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~10  = ~ \acl_work_group_dispatcher:group_dispatcher|Equal2~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal11~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal8~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[3]~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[5]~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[4]~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[15]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[6]~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[21]~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[13]~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[23]~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[15]~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[7]~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[22]~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[14]~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[20]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[12]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal6~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~32  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~31  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~30  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~28  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~27  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~26  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[19]~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[8]~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[23]~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[9]~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[12]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[3]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[5]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[4]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[6]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[7]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[16]~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[6]~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[9]~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[8]~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[4]~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[5]~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal20~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[1]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~26  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[0]~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[2]~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[1]~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[14]~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[15]~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[18]~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[17]~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[19]~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[7]~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[10]~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[11]~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[12]~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[13]~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[3]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or263_i[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__31_i  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal21~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_11_i  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__SFC_1_VALID_165_166_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[31]  = ~ \workgroup_size_NO_SHIFT_REG[31] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[30]  = ~ \workgroup_size_NO_SHIFT_REG[30] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[28]  = ~ \workgroup_size_NO_SHIFT_REG[28] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[27]  = ~ \workgroup_size_NO_SHIFT_REG[27] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[26]  = ~ \workgroup_size_NO_SHIFT_REG[26] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[25]  = ~ \workgroup_size_NO_SHIFT_REG[25] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[24]  = ~ \workgroup_size_NO_SHIFT_REG[24] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[29]  = ~ \workgroup_size_NO_SHIFT_REG[29] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[23]  = ~ \workgroup_size_NO_SHIFT_REG[23] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[22]  = ~ \workgroup_size_NO_SHIFT_REG[22] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[20]  = ~ \workgroup_size_NO_SHIFT_REG[20] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[19]  = ~ \workgroup_size_NO_SHIFT_REG[19] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[18]  = ~ \workgroup_size_NO_SHIFT_REG[18] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[17]  = ~ \workgroup_size_NO_SHIFT_REG[17] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[16]  = ~ \workgroup_size_NO_SHIFT_REG[16] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[21]  = ~ \workgroup_size_NO_SHIFT_REG[21] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[15]  = ~ \workgroup_size_NO_SHIFT_REG[15] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[14]  = ~ \workgroup_size_NO_SHIFT_REG[14] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[12]  = ~ \workgroup_size_NO_SHIFT_REG[12] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[11]  = ~ \workgroup_size_NO_SHIFT_REG[11] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[10]  = ~ \workgroup_size_NO_SHIFT_REG[10] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[9]  = ~ \workgroup_size_NO_SHIFT_REG[9] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[8]  = ~ \workgroup_size_NO_SHIFT_REG[8] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[13]  = ~ \workgroup_size_NO_SHIFT_REG[13] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[7]  = ~ \workgroup_size_NO_SHIFT_REG[7] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[6]  = ~ \workgroup_size_NO_SHIFT_REG[6] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[4]  = ~ \workgroup_size_NO_SHIFT_REG[4] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[3]  = ~ \workgroup_size_NO_SHIFT_REG[3] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[2]  = ~ \workgroup_size_NO_SHIFT_REG[2] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[1]  = ~ \workgroup_size_NO_SHIFT_REG[1] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[0]  = ~ \workgroup_size_NO_SHIFT_REG[0] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__completed_items_incr[0]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0] ;
assign \__ALT_INV__workgroup_size_NO_SHIFT_REG[5]  = ~ \workgroup_size_NO_SHIFT_REG[5] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][22]  = ~ \num_groups_NO_SHIFT_REG[2][22] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][21]  = ~ \num_groups_NO_SHIFT_REG[2][21] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][19]  = ~ \num_groups_NO_SHIFT_REG[2][19] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][18]  = ~ \num_groups_NO_SHIFT_REG[2][18] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][23]  = ~ \num_groups_NO_SHIFT_REG[2][23] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][20]  = ~ \num_groups_NO_SHIFT_REG[2][20] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][25]  = ~ \num_groups_NO_SHIFT_REG[2][25] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][24]  = ~ \num_groups_NO_SHIFT_REG[2][24] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][26]  = ~ \num_groups_NO_SHIFT_REG[2][26] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][28]  = ~ \num_groups_NO_SHIFT_REG[2][28] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][27]  = ~ \num_groups_NO_SHIFT_REG[2][27] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][31]  = ~ \num_groups_NO_SHIFT_REG[2][31] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][30]  = ~ \num_groups_NO_SHIFT_REG[2][30] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][29]  = ~ \num_groups_NO_SHIFT_REG[2][29] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][4]  = ~ \num_groups_NO_SHIFT_REG[2][4] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][3]  = ~ \num_groups_NO_SHIFT_REG[2][3] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][1]  = ~ \num_groups_NO_SHIFT_REG[2][1] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][5]  = ~ \num_groups_NO_SHIFT_REG[2][5] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][2]  = ~ \num_groups_NO_SHIFT_REG[2][2] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][7]  = ~ \num_groups_NO_SHIFT_REG[2][7] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][6]  = ~ \num_groups_NO_SHIFT_REG[2][6] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][8]  = ~ \num_groups_NO_SHIFT_REG[2][8] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][10]  = ~ \num_groups_NO_SHIFT_REG[2][10] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][9]  = ~ \num_groups_NO_SHIFT_REG[2][9] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][11]  = ~ \num_groups_NO_SHIFT_REG[2][11] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][13]  = ~ \num_groups_NO_SHIFT_REG[2][13] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][12]  = ~ \num_groups_NO_SHIFT_REG[2][12] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][14]  = ~ \num_groups_NO_SHIFT_REG[2][14] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][16]  = ~ \num_groups_NO_SHIFT_REG[2][16] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][15]  = ~ \num_groups_NO_SHIFT_REG[2][15] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[2][17]  = ~ \num_groups_NO_SHIFT_REG[2][17] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][22]  = ~ \num_groups_NO_SHIFT_REG[1][22] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][21]  = ~ \num_groups_NO_SHIFT_REG[1][21] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][19]  = ~ \num_groups_NO_SHIFT_REG[1][19] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][18]  = ~ \num_groups_NO_SHIFT_REG[1][18] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][23]  = ~ \num_groups_NO_SHIFT_REG[1][23] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][20]  = ~ \num_groups_NO_SHIFT_REG[1][20] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][25]  = ~ \num_groups_NO_SHIFT_REG[1][25] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][24]  = ~ \num_groups_NO_SHIFT_REG[1][24] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][26]  = ~ \num_groups_NO_SHIFT_REG[1][26] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][28]  = ~ \num_groups_NO_SHIFT_REG[1][28] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][27]  = ~ \num_groups_NO_SHIFT_REG[1][27] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][31]  = ~ \num_groups_NO_SHIFT_REG[1][31] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][30]  = ~ \num_groups_NO_SHIFT_REG[1][30] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][29]  = ~ \num_groups_NO_SHIFT_REG[1][29] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][4]  = ~ \num_groups_NO_SHIFT_REG[1][4] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][3]  = ~ \num_groups_NO_SHIFT_REG[1][3] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][1]  = ~ \num_groups_NO_SHIFT_REG[1][1] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][5]  = ~ \num_groups_NO_SHIFT_REG[1][5] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][2]  = ~ \num_groups_NO_SHIFT_REG[1][2] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][7]  = ~ \num_groups_NO_SHIFT_REG[1][7] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][6]  = ~ \num_groups_NO_SHIFT_REG[1][6] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][8]  = ~ \num_groups_NO_SHIFT_REG[1][8] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][10]  = ~ \num_groups_NO_SHIFT_REG[1][10] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][9]  = ~ \num_groups_NO_SHIFT_REG[1][9] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][11]  = ~ \num_groups_NO_SHIFT_REG[1][11] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][13]  = ~ \num_groups_NO_SHIFT_REG[1][13] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][12]  = ~ \num_groups_NO_SHIFT_REG[1][12] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][14]  = ~ \num_groups_NO_SHIFT_REG[1][14] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][16]  = ~ \num_groups_NO_SHIFT_REG[1][16] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][15]  = ~ \num_groups_NO_SHIFT_REG[1][15] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[1][17]  = ~ \num_groups_NO_SHIFT_REG[1][17] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][22]  = ~ \num_groups_NO_SHIFT_REG[0][22] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][21]  = ~ \num_groups_NO_SHIFT_REG[0][21] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][19]  = ~ \num_groups_NO_SHIFT_REG[0][19] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][18]  = ~ \num_groups_NO_SHIFT_REG[0][18] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][23]  = ~ \num_groups_NO_SHIFT_REG[0][23] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][20]  = ~ \num_groups_NO_SHIFT_REG[0][20] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][25]  = ~ \num_groups_NO_SHIFT_REG[0][25] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][24]  = ~ \num_groups_NO_SHIFT_REG[0][24] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][26]  = ~ \num_groups_NO_SHIFT_REG[0][26] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][28]  = ~ \num_groups_NO_SHIFT_REG[0][28] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][27]  = ~ \num_groups_NO_SHIFT_REG[0][27] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][31]  = ~ \num_groups_NO_SHIFT_REG[0][31] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][30]  = ~ \num_groups_NO_SHIFT_REG[0][30] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][29]  = ~ \num_groups_NO_SHIFT_REG[0][29] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][4]  = ~ \num_groups_NO_SHIFT_REG[0][4] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][3]  = ~ \num_groups_NO_SHIFT_REG[0][3] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][1]  = ~ \num_groups_NO_SHIFT_REG[0][1] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][5]  = ~ \num_groups_NO_SHIFT_REG[0][5] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][2]  = ~ \num_groups_NO_SHIFT_REG[0][2] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][7]  = ~ \num_groups_NO_SHIFT_REG[0][7] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][6]  = ~ \num_groups_NO_SHIFT_REG[0][6] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][8]  = ~ \num_groups_NO_SHIFT_REG[0][8] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][10]  = ~ \num_groups_NO_SHIFT_REG[0][10] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][9]  = ~ \num_groups_NO_SHIFT_REG[0][9] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][11]  = ~ \num_groups_NO_SHIFT_REG[0][11] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][13]  = ~ \num_groups_NO_SHIFT_REG[0][13] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][12]  = ~ \num_groups_NO_SHIFT_REG[0][12] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][14]  = ~ \num_groups_NO_SHIFT_REG[0][14] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][16]  = ~ \num_groups_NO_SHIFT_REG[0][16] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][15]  = ~ \num_groups_NO_SHIFT_REG[0][15] ;
assign \__ALT_INV__num_groups_NO_SHIFT_REG[0][17]  = ~ \num_groups_NO_SHIFT_REG[0][17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[156]  = ~ \kernel_arguments_NO_SHIFT_REG[156] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[155]  = ~ \kernel_arguments_NO_SHIFT_REG[155] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[158]  = ~ \kernel_arguments_NO_SHIFT_REG[158] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[157]  = ~ \kernel_arguments_NO_SHIFT_REG[157] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[150]  = ~ \kernel_arguments_NO_SHIFT_REG[150] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[149]  = ~ \kernel_arguments_NO_SHIFT_REG[149] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[152]  = ~ \kernel_arguments_NO_SHIFT_REG[152] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[151]  = ~ \kernel_arguments_NO_SHIFT_REG[151] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[154]  = ~ \kernel_arguments_NO_SHIFT_REG[154] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[153]  = ~ \kernel_arguments_NO_SHIFT_REG[153] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[145]  = ~ \kernel_arguments_NO_SHIFT_REG[145] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[144]  = ~ \kernel_arguments_NO_SHIFT_REG[144] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[143]  = ~ \kernel_arguments_NO_SHIFT_REG[143] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[147]  = ~ \kernel_arguments_NO_SHIFT_REG[147] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[146]  = ~ \kernel_arguments_NO_SHIFT_REG[146] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[138]  = ~ \kernel_arguments_NO_SHIFT_REG[138] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[140]  = ~ \kernel_arguments_NO_SHIFT_REG[140] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[139]  = ~ \kernel_arguments_NO_SHIFT_REG[139] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[142]  = ~ \kernel_arguments_NO_SHIFT_REG[142] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[141]  = ~ \kernel_arguments_NO_SHIFT_REG[141] ;
assign \__ALT_INV__kernel_arguments_NO_SHIFT_REG[148]  = ~ \kernel_arguments_NO_SHIFT_REG[148] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4] ;
assign \acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group  = ~ \acl_id_iterator:id_iter_inst0|just_seen_last_in_group ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][23]  = ~ \local_size_NO_SHIFT_REG[1][23] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][22]  = ~ \local_size_NO_SHIFT_REG[1][22] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][21]  = ~ \local_size_NO_SHIFT_REG[1][21] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][20]  = ~ \local_size_NO_SHIFT_REG[1][20] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][19]  = ~ \local_size_NO_SHIFT_REG[1][19] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][18]  = ~ \local_size_NO_SHIFT_REG[1][18] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][26]  = ~ \local_size_NO_SHIFT_REG[1][26] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][25]  = ~ \local_size_NO_SHIFT_REG[1][25] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][24]  = ~ \local_size_NO_SHIFT_REG[1][24] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][29]  = ~ \local_size_NO_SHIFT_REG[1][29] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][28]  = ~ \local_size_NO_SHIFT_REG[1][28] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][27]  = ~ \local_size_NO_SHIFT_REG[1][27] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][31]  = ~ \local_size_NO_SHIFT_REG[1][31] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][30]  = ~ \local_size_NO_SHIFT_REG[1][30] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][5]  = ~ \local_size_NO_SHIFT_REG[1][5] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][4]  = ~ \local_size_NO_SHIFT_REG[1][4] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][3]  = ~ \local_size_NO_SHIFT_REG[1][3] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][2]  = ~ \local_size_NO_SHIFT_REG[1][2] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][1]  = ~ \local_size_NO_SHIFT_REG[1][1] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][8]  = ~ \local_size_NO_SHIFT_REG[1][8] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][7]  = ~ \local_size_NO_SHIFT_REG[1][7] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][6]  = ~ \local_size_NO_SHIFT_REG[1][6] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][11]  = ~ \local_size_NO_SHIFT_REG[1][11] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][10]  = ~ \local_size_NO_SHIFT_REG[1][10] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][9]  = ~ \local_size_NO_SHIFT_REG[1][9] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][14]  = ~ \local_size_NO_SHIFT_REG[1][14] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][13]  = ~ \local_size_NO_SHIFT_REG[1][13] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][12]  = ~ \local_size_NO_SHIFT_REG[1][12] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][17]  = ~ \local_size_NO_SHIFT_REG[1][17] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][16]  = ~ \local_size_NO_SHIFT_REG[1][16] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[1][15]  = ~ \local_size_NO_SHIFT_REG[1][15] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][23]  = ~ \local_size_NO_SHIFT_REG[0][23] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][22]  = ~ \local_size_NO_SHIFT_REG[0][22] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][21]  = ~ \local_size_NO_SHIFT_REG[0][21] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][20]  = ~ \local_size_NO_SHIFT_REG[0][20] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][19]  = ~ \local_size_NO_SHIFT_REG[0][19] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][18]  = ~ \local_size_NO_SHIFT_REG[0][18] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][26]  = ~ \local_size_NO_SHIFT_REG[0][26] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][25]  = ~ \local_size_NO_SHIFT_REG[0][25] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][24]  = ~ \local_size_NO_SHIFT_REG[0][24] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][29]  = ~ \local_size_NO_SHIFT_REG[0][29] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][28]  = ~ \local_size_NO_SHIFT_REG[0][28] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][27]  = ~ \local_size_NO_SHIFT_REG[0][27] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][31]  = ~ \local_size_NO_SHIFT_REG[0][31] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][30]  = ~ \local_size_NO_SHIFT_REG[0][30] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][5]  = ~ \local_size_NO_SHIFT_REG[0][5] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][4]  = ~ \local_size_NO_SHIFT_REG[0][4] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][3]  = ~ \local_size_NO_SHIFT_REG[0][3] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][2]  = ~ \local_size_NO_SHIFT_REG[0][2] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][1]  = ~ \local_size_NO_SHIFT_REG[0][1] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][8]  = ~ \local_size_NO_SHIFT_REG[0][8] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][7]  = ~ \local_size_NO_SHIFT_REG[0][7] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][6]  = ~ \local_size_NO_SHIFT_REG[0][6] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][11]  = ~ \local_size_NO_SHIFT_REG[0][11] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][10]  = ~ \local_size_NO_SHIFT_REG[0][10] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][9]  = ~ \local_size_NO_SHIFT_REG[0][9] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][14]  = ~ \local_size_NO_SHIFT_REG[0][14] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][13]  = ~ \local_size_NO_SHIFT_REG[0][13] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][12]  = ~ \local_size_NO_SHIFT_REG[0][12] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][17]  = ~ \local_size_NO_SHIFT_REG[0][17] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][16]  = ~ \local_size_NO_SHIFT_REG[0][16] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[0][15]  = ~ \local_size_NO_SHIFT_REG[0][15] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][23]  = ~ \local_size_NO_SHIFT_REG[2][23] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][22]  = ~ \local_size_NO_SHIFT_REG[2][22] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][21]  = ~ \local_size_NO_SHIFT_REG[2][21] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][20]  = ~ \local_size_NO_SHIFT_REG[2][20] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][19]  = ~ \local_size_NO_SHIFT_REG[2][19] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][18]  = ~ \local_size_NO_SHIFT_REG[2][18] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][26]  = ~ \local_size_NO_SHIFT_REG[2][26] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][25]  = ~ \local_size_NO_SHIFT_REG[2][25] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][24]  = ~ \local_size_NO_SHIFT_REG[2][24] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][29]  = ~ \local_size_NO_SHIFT_REG[2][29] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][28]  = ~ \local_size_NO_SHIFT_REG[2][28] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][27]  = ~ \local_size_NO_SHIFT_REG[2][27] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][31]  = ~ \local_size_NO_SHIFT_REG[2][31] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][30]  = ~ \local_size_NO_SHIFT_REG[2][30] ;
assign \__ALT_INV__local_size_NO_SHIFT_REG[2][5]  = ~ \local_size_NO_SHIFT_REG[2][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[8]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|__ALT_INV__has_a_lsu_active~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][213]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][213]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][121]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][83]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][25]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][23]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][21]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][11]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][10]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][14]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][18]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][7]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][6]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][4]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5]~DUPLICATE  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12]~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17]~DUPLICATE  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~DUPLICATE  = ~ \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_inputs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__inputs_ready  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|__ALT_INV__o_active  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active ;
assign __ALT_INV__started_NO_SHIFT_REG = ~ started_NO_SHIFT_REG;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__empty_dff  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff ;
assign __ALT_INV__start_NO_SHIFT_REG = ~ start_NO_SHIFT_REG;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_2~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Equal1~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ;
assign \__ALT_INV__status_NO_SHIFT_REG[15]  = ~ \status_NO_SHIFT_REG[15] ;
assign \__ALT_INV__status_NO_SHIFT_REG[14]  = ~ \status_NO_SHIFT_REG[14] ;
assign \__ALT_INV__status_NO_SHIFT_REG[13]  = ~ \status_NO_SHIFT_REG[13] ;
assign \__ALT_INV__status_NO_SHIFT_REG[10]  = ~ \status_NO_SHIFT_REG[10] ;
assign \__ALT_INV__status_NO_SHIFT_REG[9]  = ~ \status_NO_SHIFT_REG[9] ;
assign \__ALT_INV__status_NO_SHIFT_REG[8]  = ~ \status_NO_SHIFT_REG[8] ;
assign \__ALT_INV__status_NO_SHIFT_REG[7]  = ~ \status_NO_SHIFT_REG[7] ;
assign \__ALT_INV__status_NO_SHIFT_REG[6]  = ~ \status_NO_SHIFT_REG[6] ;
assign \__ALT_INV__status_NO_SHIFT_REG[5]  = ~ \status_NO_SHIFT_REG[5] ;
assign \__ALT_INV__status_NO_SHIFT_REG[4]  = ~ \status_NO_SHIFT_REG[4] ;
assign \__ALT_INV__status_NO_SHIFT_REG[2]  = ~ \status_NO_SHIFT_REG[2] ;
assign \__ALT_INV__WideOr1~0  = ~ \WideOr1~0 ;
assign \__ALT_INV__status_NO_SHIFT_REG[0]  = ~ \status_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__write_accepted  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish  = ~ \acl_kernel_finish_detector:kernel_finish_detector|finish ;
assign \__ALT_INV__status_NO_SHIFT_REG[3]~1  = ~ \status_NO_SHIFT_REG[3]~1 ;
assign __ALT_INV__cra_read_st1_NO_SHIFT_REG = ~ cra_read_st1_NO_SHIFT_REG;
assign \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[16]  = ~ \cra_readdata_st1_NO_SHIFT_REG[16] ;
assign \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[15]  = ~ \cra_readdata_st1_NO_SHIFT_REG[15] ;
assign \__ALT_INV__avs_cra_readdata~0  = ~ \avs_cra_readdata~0 ;
assign \__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[12]  = ~ \cra_readdata_st1_NO_SHIFT_REG[12] ;
assign \__ALT_INV__Equal0~0  = ~ \Equal0~0 ;
assign \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[0]  = ~ \cra_addr_st1_NO_SHIFT_REG[0] ;
assign \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[1]  = ~ \cra_addr_st1_NO_SHIFT_REG[1] ;
assign \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[2]  = ~ \cra_addr_st1_NO_SHIFT_REG[2] ;
assign \__ALT_INV__cra_addr_st1_NO_SHIFT_REG[3]  = ~ \cra_addr_st1_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[4]~30  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[3]~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[2]~28  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[1]~27  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[0]~26  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][287]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][287] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[287]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[287] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][286]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][286] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[286]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[286] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][285]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][285] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[285]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[285] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][284]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][284] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[284]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[284] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][283]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][283] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[283]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[283] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][282]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][282] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[282]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[282] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][281]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][281] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[281]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[281] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][280]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][280] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[280]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[280] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][279]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][279] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[279]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[279] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][278]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][278] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[278]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[278] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][277]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][277] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[277]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[277] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][276]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][276] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[276]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[276] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][275]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][275] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[275]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[275] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][274]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][274] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[274]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[274] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][273]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][273] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[273]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[273] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][272]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][272] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[272]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[272] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][271]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][271] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[271]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[271] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][270]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][270] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[270]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[270] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][269]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][269] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[269]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[269] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][268]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][268] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[268]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[268] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][267]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][267] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[267]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[267] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][266]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][266] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[266]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[266] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][265]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][265] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[265]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[265] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][264]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][264] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[264]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[264] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][263]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][263] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[263]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[263] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][262]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][262] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[262]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[262] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][261]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][261] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[261]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[261] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][260]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][260] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[260]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[260] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][259]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][259] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[259]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[259] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][258]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][258] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[258]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[258] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][257]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][257] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[257]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[257] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][256]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][256] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[256]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[256] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][255]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][255] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[255]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[255] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][254]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][254] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[254]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[254] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][253]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][253] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[253]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[253] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][252]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][252] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[252]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[252] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][251]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][251] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[251]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[251] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][250]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][250] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[250]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[250] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][249]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][249] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[249]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[249] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][248]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][248] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[248]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[248] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][247]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][247] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[247]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[247] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][246]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][246] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[246]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[246] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][245]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][245] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[245]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[245] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][244]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][244] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[244]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[244] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][243]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][243] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[243]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[243] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][242]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][242] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[242]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[242] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][241]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][241] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[241]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[241] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][240]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][240] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[240]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[240] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][239]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][239] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[239]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[239] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][238]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][238] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[238]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[238] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][237]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][237] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[237]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[237] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][236]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][236] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[236]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[236] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][235]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][235] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[235]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[235] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][234]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][234] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[234]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[234] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][233]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][233] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[233]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[233] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][232]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][232] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[232]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[232] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][231]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][231] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[231]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[231] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][230]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][230] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[230]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[230] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][229]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][229] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[229]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[229] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][228]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][228] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[228]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[228] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][227]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][227] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[227]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[227] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][226]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][226] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[226]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[226] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][225]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][225] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[225]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[225] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][224]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][224] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[224]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[224] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][223]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][223] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[223]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[223] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][222]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][222] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[222]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[222] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[3]~37  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[2]~33  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[1]~29  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[5]~25  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[4]~21  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[0]~1  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1 ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][47]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][47]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][46]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][44]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][43]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][42]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][42]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][41]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][41]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][40]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][40]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][45]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][45]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][39]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][39]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][36]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][36]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][35]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][35]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][34]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][34]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][32]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][32]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][37]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][31]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][31]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][30]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][27]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][27]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][26]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][26]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][25]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][24]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][29]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][29]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][23]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][22]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][22]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][18]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][17]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][17]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][16]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][16]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][15]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][14]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][14]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][12]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][11]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][9]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][8]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][8]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][13]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][95]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][95]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][94]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][94]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][92]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][92]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][91]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][91]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][90]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][90]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][89]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][89]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][88]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][87]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][86]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][84]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][83]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][82]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][82]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][81]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][81]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][80]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][85]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][79]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][78]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][76]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][75]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][74]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][72]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][77]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][77]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][70]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][70]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][68]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][65]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][65]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][63]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][62]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][62]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][60]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][58]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][58]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][57]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][57]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][56]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][61]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][54]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][54]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][52]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][52]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][51]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][51]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][50]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][50]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][49]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][48]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][53]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][6]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][4]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][4]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][0]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[2][17] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[1][17] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][22] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][21]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][21] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][19] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][18]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][18] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][23]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][23] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][20] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][25]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][25] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][24] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][26] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][28] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][27] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][31] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][30]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][30] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][29] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][4] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][3] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][0] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][5] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][2] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][7]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][7] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][6] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][8] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][10]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][10] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][9] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][11]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][11] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][13] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][12] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][14]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][14] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][16] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|group_id[0][17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[5]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[4]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[3]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[2]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[1]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[11]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[10]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[9]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[8]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[7]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[6]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[0]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[29]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[30]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups  = ~ \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__cmp_result_reg  = ~ \acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__pipelined_dispatched_all_groups[2]  = ~ \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_byteenable[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_byteenable[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~69  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~61  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~53  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~45  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~37  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][1]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1] ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][0]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add2~29  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~113  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~113  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~113  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][2]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~21  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][1]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[1]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[2]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[3]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[4]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[4] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[5]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[5] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[6]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[6] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[7]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[7] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[8]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[8] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[9]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[9] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[10]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[10] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[11]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[11] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[12]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[12] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[13]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[13] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[14]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[14] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[15]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[15] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[16]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[16] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[17]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[17] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[18]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[18] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[19]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[19] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[20]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[20] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[21]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[21] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[22]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[22] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[23]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[23] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[24]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[24] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[25]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[25] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[26]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[26] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[27]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[27] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[28]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[0]  = ~ \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~109  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~109  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~109  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~105  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~105  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~105  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][24]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~101  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~101  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~101  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~97  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~97  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~97  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][22]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~93  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~93  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~93  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~89  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~89  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~89  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][28]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~85  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~85  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~85  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][27]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~81  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~81  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~81  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][26]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~77  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~77  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~77  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][8]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~73  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~73  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~73  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~69  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~69  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~69  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~65  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~65  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~65  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~61  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~61  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~61  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][9]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~57  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~57  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~57  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~53  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~53  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~53  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][13]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~49  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~49  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~49  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][12]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~45  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~45  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~45  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][17]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~41  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~41  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~41  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][16]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~37  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][4]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][3]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~17  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~13  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~9  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~37  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~33  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~29  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~25  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~21  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~17  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~13  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~9  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~5  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5 ;
assign \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~1  = ~ \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][221]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][221] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[221]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[221] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][220]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][220] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[220]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[220] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][219]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][219] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[219]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[219] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][218]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][218] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[218]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[218] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][217]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][217] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[217]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[217] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][216]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][216] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[216]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[216] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][215]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][215] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[215]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[215] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][214]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][214] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[214]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[214] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[213]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[213] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][212]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][212] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[212]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[212] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][211]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][211] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[211]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[211] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][210]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][210] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[210]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[210] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][209]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][209] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[209]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[209] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][208]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][208] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[208]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[208] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][207]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][207] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[207]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[207] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][206]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][206] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[206]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[206] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][205]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][205] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[205]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[205] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][204]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][204] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[204]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[204] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][203]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][203] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[203]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[203] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][202]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][202] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[202]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[202] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][201]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][201] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[201]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[201] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][200]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][200] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[200]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[200] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][199]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][199] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[199]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[199] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][198]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][198] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[198]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[198] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][197]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][197] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[197]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[197] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][196]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][196] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[196]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[196] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][195]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][195] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[195]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[195] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][194]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][194] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[194]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[194] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][193]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][193] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[193]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[193] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][192]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][192] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[192]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[192] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][191]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[191]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][190]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[190]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][189]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[189]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][188]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[188]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][187]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[187]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][186]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[186]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][185]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[185]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][184]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[184]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][183]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[183]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][182]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[182]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][181]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[181]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][180]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[180]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][179]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[179]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][178]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[178]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][177]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[177]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][176]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[176]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][175]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[175]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][174]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[174]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][173]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[173]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][172]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[172]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][171]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[171]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][170]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[170]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][169]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[169]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][168]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[168]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][167]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[167]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][166]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[166]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][165]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[165]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][164]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[164]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][163]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[163]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][162]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[162]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][161]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[161]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][160]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[160]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][159]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[159]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][158]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[158]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][157]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[157]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][156]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[156]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][155]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[155]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][154]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[154]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][153]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[153]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][152]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[152]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][151]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[151]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][150]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[150]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][149]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[149]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][148]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[148]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][147]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[147]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][146]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[146]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][145]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[145]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][144]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[144]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][143]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[143]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][142]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[142]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][141]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[141]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][140]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[140]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][139]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[139]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][138]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[138]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][137]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[137]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][136]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[136]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][135]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[135]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][134]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[134]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][133]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[133]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][132]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[132]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][131]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[131]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][130]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[130]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][129]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[129]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][128]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[128]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][127]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[127]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][126]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[126]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][125]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[125]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][124]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[124]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][123]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[123]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][122]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[122]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[121]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][120]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[120]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][119]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[119]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][118]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[118]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][117]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[117]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][116]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[116]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][115]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[115]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][114]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[114]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][113]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[113]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][112]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[112]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][111]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[111]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][110]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[110]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][109]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[109]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][108]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[108]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][107]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[107]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][106]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[106]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][105]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[105]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][104]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[104]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][103]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[103]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][102]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[102]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][101]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[101]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][100]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[100]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][99]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[99]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][98]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[98]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][97]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[97]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][96]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[96]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][95]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[95]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][86]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[86]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[83]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][82]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[82]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][81]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[81]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][80]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[80]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][73]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[73]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][67]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[67]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][65]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[65]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_valid~0  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;
assign \__ALT_INV__status_NO_SHIFT_REG[1]  = ~ \status_NO_SHIFT_REG[1] ;
assign \__ALT_INV__status_NO_SHIFT_REG[3]  = ~ \status_NO_SHIFT_REG[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~26  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~33  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish_asserted  = ~ \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted ;
assign \acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__ndrange_done  = ~ \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[6]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[6] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[9]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[9] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[13]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[13] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[18]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[20]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[20] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[22]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[22] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[23]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[23] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[24]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[24] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[25]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[25] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[26]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[26] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[28]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[28] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[29]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[29] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[30]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[30] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[1]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[1] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[11]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[11] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[15]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[15] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[16]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[16] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[17]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[17] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[19]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[19] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[21]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[21] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[272]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[272] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[274]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[274] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[278]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[278] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[279]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[279] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[280]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[280] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[281]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[281] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[282]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[282] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[283]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[283] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[284]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[284] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[286]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[286] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[287]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[287] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[0]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[0] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[233]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[233] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[236]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[236] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[237]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[237] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[238]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[238] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[239]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[239] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[243]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[243] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[244]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[244] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[245]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[245] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[246]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[246] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[247]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[247] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[248]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[248] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[249]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[249] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[250]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[250] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[251]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[251] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[252]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[252] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[253]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[253] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[254]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[254] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[257]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[257] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[258]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[258] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[261]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[261] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[262]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[262] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[263]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[263] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[266]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[266] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[267]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[267] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[268]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[268] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[269]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[269] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[270]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[270] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[271]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[271] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[232]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[232] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[193]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[193] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[196]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[196] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[198]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[198] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[203]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[203] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[205]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[205] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[206]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[206] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[207]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[207] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[208]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[208] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[209]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[209] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[212]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[212] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[213]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[213] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[214]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[214] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[215]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[215] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[216]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[216] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[218]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[218] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[220]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[220] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[222]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[222] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[223]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[223] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[224]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[224] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[225]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[225] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[227]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[227] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[229]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[229] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[231]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[231] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[153]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[153] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[155]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[155] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[157]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[157] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[158]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[158] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[161]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[161] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[162]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[162] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[163]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[163] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[164]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[164] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[165]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[165] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[166]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[166] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[167]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[167] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[169]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[169] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[171]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[171] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[172]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[172] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[173]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[173] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[175]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[175] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[177]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[177] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[178]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[178] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[179]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[179] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[180]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[180] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[182]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[182] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[183]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[183] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[184]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[184] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[186]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[186] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[187]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[187] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[189]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[189] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[190]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[190] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[191]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[191] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[113]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[113] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[114]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[114] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[116]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[116] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[118]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[118] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[119]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[119] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[120]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[120] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[121]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[121] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[123]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[123] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[124]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[124] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[127]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[127] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[128]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[128] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[129]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[129] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[130]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[130] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[133]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[133] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[135]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[135] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[136]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[136] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[137]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[137] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[140]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[140] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[141]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[141] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[142]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[142] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[144]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[144] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[145]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[145] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[147]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[147] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[149]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[149] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[150]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[150] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[112]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[112] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[74]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[74] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[75]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[75] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[76]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[76] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[77]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[77] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[78]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[78] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[79]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[79] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[83]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[83] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[84]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[84] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[85]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[85] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[87]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[87] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[88]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[88] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[89]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[89] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[90]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[90] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[91]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[91] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[92]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[92] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[93]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[93] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[94]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[94] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[96]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[96] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[97]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[97] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[98]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[98] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[100]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[100] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[101]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[101] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[102]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[102] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[104]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[104] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[106]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[106] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[107]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[107] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[108]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[108] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[109]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[109] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[110]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[110] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[72]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[72] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[33]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[33] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[34]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[34] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[35]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[35] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[38]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[38] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[39]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[39] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[40]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[40] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[42]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[42] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[43]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[43] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[44]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[44] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[45]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[45] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[47]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[47] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[48]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[48] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[49]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[49] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[50]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[50] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[51]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[51] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[52]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[52] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[53]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[53] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[55]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[55] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[57]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[57] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[58]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[58] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[60]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[60] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[61]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[61] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[62]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[62] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[63]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[63] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[64]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[64] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[66]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[66] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[68]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[68] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[69]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[69] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[70]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[70] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[71]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[71] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[32]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[32] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~37  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~37  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][15]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~33  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~33  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~33  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][20]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~29  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~29  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~29  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][19]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~25  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~25  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~25  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~21  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~21  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~21  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~5  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5 ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][24]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][23]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][22]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][21]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][28]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][27]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][26]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~17  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~17  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~17  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~13  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~13  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~13  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][5]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~9  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~5  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5 ;
assign \acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][3]  = ~ \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~1  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1 ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][11]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][10]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][9]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][14]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][13]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][12]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][17]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][16]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][15]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][20]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][19]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19] ;
assign \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][18]  = ~ \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] ;
assign \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8]  = ~ \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] ;

assign avs_cra_readdata[0] = \avs_cra_readdata[0]~reg0 ;

assign avs_cra_readdata[1] = \avs_cra_readdata[1]~reg0 ;

assign avs_cra_readdata[2] = \avs_cra_readdata[2]~reg0 ;

assign avs_cra_readdata[3] = \avs_cra_readdata[3]~reg0 ;

assign avs_cra_readdata[4] = \avs_cra_readdata[4]~reg0 ;

assign avs_cra_readdata[5] = \avs_cra_readdata[5]~reg0 ;

assign avs_cra_readdata[6] = \avs_cra_readdata[6]~reg0 ;

assign avs_cra_readdata[7] = \avs_cra_readdata[7]~reg0 ;

assign avs_cra_readdata[8] = \avs_cra_readdata[8]~reg0 ;

assign avs_cra_readdata[9] = \avs_cra_readdata[9]~reg0 ;

assign avs_cra_readdata[10] = \avs_cra_readdata[10]~reg0 ;

assign avs_cra_readdata[11] = gnd;

assign avs_cra_readdata[12] = \avs_cra_readdata[12]~reg0 ;

assign avs_cra_readdata[13] = \avs_cra_readdata[13]~reg0 ;

assign avs_cra_readdata[14] = \avs_cra_readdata[14]~reg0 ;

assign avs_cra_readdata[15] = \avs_cra_readdata[15]~reg0 ;

assign avs_cra_readdata[16] = \avs_cra_readdata[16]~reg0 ;

assign avs_cra_readdata[17] = \avs_cra_readdata[17]~reg0 ;

assign avs_cra_readdata[18] = gnd;

assign avs_cra_readdata[19] = gnd;

assign avs_cra_readdata[20] = gnd;

assign avs_cra_readdata[21] = gnd;

assign avs_cra_readdata[22] = gnd;

assign avs_cra_readdata[23] = gnd;

assign avs_cra_readdata[24] = gnd;

assign avs_cra_readdata[25] = gnd;

assign avs_cra_readdata[26] = gnd;

assign avs_cra_readdata[27] = gnd;

assign avs_cra_readdata[28] = gnd;

assign avs_cra_readdata[29] = gnd;

assign avs_cra_readdata[30] = gnd;

assign avs_cra_readdata[31] = gnd;

assign avs_cra_readdata[32] = gnd;

assign avs_cra_readdata[33] = gnd;

assign avs_cra_readdata[34] = gnd;

assign avs_cra_readdata[35] = gnd;

assign avs_cra_readdata[36] = gnd;

assign avs_cra_readdata[37] = gnd;

assign avs_cra_readdata[38] = gnd;

assign avs_cra_readdata[39] = gnd;

assign avs_cra_readdata[40] = gnd;

assign avs_cra_readdata[41] = gnd;

assign avs_cra_readdata[42] = gnd;

assign avs_cra_readdata[43] = gnd;

assign avs_cra_readdata[44] = gnd;

assign avs_cra_readdata[45] = gnd;

assign avs_cra_readdata[46] = gnd;

assign avs_cra_readdata[47] = gnd;

assign avs_cra_readdata[48] = gnd;

assign avs_cra_readdata[49] = gnd;

assign avs_cra_readdata[50] = gnd;

assign avs_cra_readdata[51] = gnd;

assign avs_cra_readdata[52] = gnd;

assign avs_cra_readdata[53] = gnd;

assign avs_cra_readdata[54] = gnd;

assign avs_cra_readdata[55] = gnd;

assign avs_cra_readdata[56] = gnd;

assign avs_cra_readdata[57] = gnd;

assign avs_cra_readdata[58] = gnd;

assign avs_cra_readdata[59] = gnd;

assign avs_cra_readdata[60] = gnd;

assign avs_cra_readdata[61] = gnd;

assign avs_cra_readdata[62] = gnd;

assign avs_cra_readdata[63] = gnd;

assign avs_cra_readdatavalid = \avs_cra_readdatavalid~reg0 ;

assign cra_irq = \cra_irq~0 ;

assign avm_local_bb1_ld__inst0_enable = vcc;

assign avm_local_bb1_ld__inst0_address[0] = gnd;

assign avm_local_bb1_ld__inst0_address[1] = gnd;

assign avm_local_bb1_ld__inst0_address[2] = gnd;

assign avm_local_bb1_ld__inst0_address[3] = gnd;

assign avm_local_bb1_ld__inst0_address[4] = gnd;

assign avm_local_bb1_ld__inst0_address[5] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] ;

assign avm_local_bb1_ld__inst0_address[6] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] ;

assign avm_local_bb1_ld__inst0_address[7] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] ;

assign avm_local_bb1_ld__inst0_address[8] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] ;

assign avm_local_bb1_ld__inst0_address[9] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] ;

assign avm_local_bb1_ld__inst0_address[10] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] ;

assign avm_local_bb1_ld__inst0_address[11] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] ;

assign avm_local_bb1_ld__inst0_address[12] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] ;

assign avm_local_bb1_ld__inst0_address[13] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] ;

assign avm_local_bb1_ld__inst0_address[14] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] ;

assign avm_local_bb1_ld__inst0_address[15] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] ;

assign avm_local_bb1_ld__inst0_address[16] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] ;

assign avm_local_bb1_ld__inst0_address[17] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] ;

assign avm_local_bb1_ld__inst0_address[18] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] ;

assign avm_local_bb1_ld__inst0_address[19] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] ;

assign avm_local_bb1_ld__inst0_address[20] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] ;

assign avm_local_bb1_ld__inst0_address[21] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] ;

assign avm_local_bb1_ld__inst0_address[22] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] ;

assign avm_local_bb1_ld__inst0_address[23] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] ;

assign avm_local_bb1_ld__inst0_address[24] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] ;

assign avm_local_bb1_ld__inst0_address[25] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] ;

assign avm_local_bb1_ld__inst0_address[26] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] ;

assign avm_local_bb1_ld__inst0_address[27] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] ;

assign avm_local_bb1_ld__inst0_address[28] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] ;

assign avm_local_bb1_ld__inst0_address[29] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] ;

assign avm_local_bb1_ld__inst0_address[30] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] ;

assign avm_local_bb1_ld__inst0_read = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;

assign avm_local_bb1_ld__inst0_write = gnd;

assign avm_local_bb1_ld__inst0_writedata[0] = gnd;

assign avm_local_bb1_ld__inst0_writedata[1] = gnd;

assign avm_local_bb1_ld__inst0_writedata[2] = gnd;

assign avm_local_bb1_ld__inst0_writedata[3] = gnd;

assign avm_local_bb1_ld__inst0_writedata[4] = gnd;

assign avm_local_bb1_ld__inst0_writedata[5] = gnd;

assign avm_local_bb1_ld__inst0_writedata[6] = gnd;

assign avm_local_bb1_ld__inst0_writedata[7] = gnd;

assign avm_local_bb1_ld__inst0_writedata[8] = gnd;

assign avm_local_bb1_ld__inst0_writedata[9] = gnd;

assign avm_local_bb1_ld__inst0_writedata[10] = gnd;

assign avm_local_bb1_ld__inst0_writedata[11] = gnd;

assign avm_local_bb1_ld__inst0_writedata[12] = gnd;

assign avm_local_bb1_ld__inst0_writedata[13] = gnd;

assign avm_local_bb1_ld__inst0_writedata[14] = gnd;

assign avm_local_bb1_ld__inst0_writedata[15] = gnd;

assign avm_local_bb1_ld__inst0_writedata[16] = gnd;

assign avm_local_bb1_ld__inst0_writedata[17] = gnd;

assign avm_local_bb1_ld__inst0_writedata[18] = gnd;

assign avm_local_bb1_ld__inst0_writedata[19] = gnd;

assign avm_local_bb1_ld__inst0_writedata[20] = gnd;

assign avm_local_bb1_ld__inst0_writedata[21] = gnd;

assign avm_local_bb1_ld__inst0_writedata[22] = gnd;

assign avm_local_bb1_ld__inst0_writedata[23] = gnd;

assign avm_local_bb1_ld__inst0_writedata[24] = gnd;

assign avm_local_bb1_ld__inst0_writedata[25] = gnd;

assign avm_local_bb1_ld__inst0_writedata[26] = gnd;

assign avm_local_bb1_ld__inst0_writedata[27] = gnd;

assign avm_local_bb1_ld__inst0_writedata[28] = gnd;

assign avm_local_bb1_ld__inst0_writedata[29] = gnd;

assign avm_local_bb1_ld__inst0_writedata[30] = gnd;

assign avm_local_bb1_ld__inst0_writedata[31] = gnd;

assign avm_local_bb1_ld__inst0_writedata[32] = gnd;

assign avm_local_bb1_ld__inst0_writedata[33] = gnd;

assign avm_local_bb1_ld__inst0_writedata[34] = gnd;

assign avm_local_bb1_ld__inst0_writedata[35] = gnd;

assign avm_local_bb1_ld__inst0_writedata[36] = gnd;

assign avm_local_bb1_ld__inst0_writedata[37] = gnd;

assign avm_local_bb1_ld__inst0_writedata[38] = gnd;

assign avm_local_bb1_ld__inst0_writedata[39] = gnd;

assign avm_local_bb1_ld__inst0_writedata[40] = gnd;

assign avm_local_bb1_ld__inst0_writedata[41] = gnd;

assign avm_local_bb1_ld__inst0_writedata[42] = gnd;

assign avm_local_bb1_ld__inst0_writedata[43] = gnd;

assign avm_local_bb1_ld__inst0_writedata[44] = gnd;

assign avm_local_bb1_ld__inst0_writedata[45] = gnd;

assign avm_local_bb1_ld__inst0_writedata[46] = gnd;

assign avm_local_bb1_ld__inst0_writedata[47] = gnd;

assign avm_local_bb1_ld__inst0_writedata[48] = gnd;

assign avm_local_bb1_ld__inst0_writedata[49] = gnd;

assign avm_local_bb1_ld__inst0_writedata[50] = gnd;

assign avm_local_bb1_ld__inst0_writedata[51] = gnd;

assign avm_local_bb1_ld__inst0_writedata[52] = gnd;

assign avm_local_bb1_ld__inst0_writedata[53] = gnd;

assign avm_local_bb1_ld__inst0_writedata[54] = gnd;

assign avm_local_bb1_ld__inst0_writedata[55] = gnd;

assign avm_local_bb1_ld__inst0_writedata[56] = gnd;

assign avm_local_bb1_ld__inst0_writedata[57] = gnd;

assign avm_local_bb1_ld__inst0_writedata[58] = gnd;

assign avm_local_bb1_ld__inst0_writedata[59] = gnd;

assign avm_local_bb1_ld__inst0_writedata[60] = gnd;

assign avm_local_bb1_ld__inst0_writedata[61] = gnd;

assign avm_local_bb1_ld__inst0_writedata[62] = gnd;

assign avm_local_bb1_ld__inst0_writedata[63] = gnd;

assign avm_local_bb1_ld__inst0_writedata[64] = gnd;

assign avm_local_bb1_ld__inst0_writedata[65] = gnd;

assign avm_local_bb1_ld__inst0_writedata[66] = gnd;

assign avm_local_bb1_ld__inst0_writedata[67] = gnd;

assign avm_local_bb1_ld__inst0_writedata[68] = gnd;

assign avm_local_bb1_ld__inst0_writedata[69] = gnd;

assign avm_local_bb1_ld__inst0_writedata[70] = gnd;

assign avm_local_bb1_ld__inst0_writedata[71] = gnd;

assign avm_local_bb1_ld__inst0_writedata[72] = gnd;

assign avm_local_bb1_ld__inst0_writedata[73] = gnd;

assign avm_local_bb1_ld__inst0_writedata[74] = gnd;

assign avm_local_bb1_ld__inst0_writedata[75] = gnd;

assign avm_local_bb1_ld__inst0_writedata[76] = gnd;

assign avm_local_bb1_ld__inst0_writedata[77] = gnd;

assign avm_local_bb1_ld__inst0_writedata[78] = gnd;

assign avm_local_bb1_ld__inst0_writedata[79] = gnd;

assign avm_local_bb1_ld__inst0_writedata[80] = gnd;

assign avm_local_bb1_ld__inst0_writedata[81] = gnd;

assign avm_local_bb1_ld__inst0_writedata[82] = gnd;

assign avm_local_bb1_ld__inst0_writedata[83] = gnd;

assign avm_local_bb1_ld__inst0_writedata[84] = gnd;

assign avm_local_bb1_ld__inst0_writedata[85] = gnd;

assign avm_local_bb1_ld__inst0_writedata[86] = gnd;

assign avm_local_bb1_ld__inst0_writedata[87] = gnd;

assign avm_local_bb1_ld__inst0_writedata[88] = gnd;

assign avm_local_bb1_ld__inst0_writedata[89] = gnd;

assign avm_local_bb1_ld__inst0_writedata[90] = gnd;

assign avm_local_bb1_ld__inst0_writedata[91] = gnd;

assign avm_local_bb1_ld__inst0_writedata[92] = gnd;

assign avm_local_bb1_ld__inst0_writedata[93] = gnd;

assign avm_local_bb1_ld__inst0_writedata[94] = gnd;

assign avm_local_bb1_ld__inst0_writedata[95] = gnd;

assign avm_local_bb1_ld__inst0_writedata[96] = gnd;

assign avm_local_bb1_ld__inst0_writedata[97] = gnd;

assign avm_local_bb1_ld__inst0_writedata[98] = gnd;

assign avm_local_bb1_ld__inst0_writedata[99] = gnd;

assign avm_local_bb1_ld__inst0_writedata[100] = gnd;

assign avm_local_bb1_ld__inst0_writedata[101] = gnd;

assign avm_local_bb1_ld__inst0_writedata[102] = gnd;

assign avm_local_bb1_ld__inst0_writedata[103] = gnd;

assign avm_local_bb1_ld__inst0_writedata[104] = gnd;

assign avm_local_bb1_ld__inst0_writedata[105] = gnd;

assign avm_local_bb1_ld__inst0_writedata[106] = gnd;

assign avm_local_bb1_ld__inst0_writedata[107] = gnd;

assign avm_local_bb1_ld__inst0_writedata[108] = gnd;

assign avm_local_bb1_ld__inst0_writedata[109] = gnd;

assign avm_local_bb1_ld__inst0_writedata[110] = gnd;

assign avm_local_bb1_ld__inst0_writedata[111] = gnd;

assign avm_local_bb1_ld__inst0_writedata[112] = gnd;

assign avm_local_bb1_ld__inst0_writedata[113] = gnd;

assign avm_local_bb1_ld__inst0_writedata[114] = gnd;

assign avm_local_bb1_ld__inst0_writedata[115] = gnd;

assign avm_local_bb1_ld__inst0_writedata[116] = gnd;

assign avm_local_bb1_ld__inst0_writedata[117] = gnd;

assign avm_local_bb1_ld__inst0_writedata[118] = gnd;

assign avm_local_bb1_ld__inst0_writedata[119] = gnd;

assign avm_local_bb1_ld__inst0_writedata[120] = gnd;

assign avm_local_bb1_ld__inst0_writedata[121] = gnd;

assign avm_local_bb1_ld__inst0_writedata[122] = gnd;

assign avm_local_bb1_ld__inst0_writedata[123] = gnd;

assign avm_local_bb1_ld__inst0_writedata[124] = gnd;

assign avm_local_bb1_ld__inst0_writedata[125] = gnd;

assign avm_local_bb1_ld__inst0_writedata[126] = gnd;

assign avm_local_bb1_ld__inst0_writedata[127] = gnd;

assign avm_local_bb1_ld__inst0_writedata[128] = gnd;

assign avm_local_bb1_ld__inst0_writedata[129] = gnd;

assign avm_local_bb1_ld__inst0_writedata[130] = gnd;

assign avm_local_bb1_ld__inst0_writedata[131] = gnd;

assign avm_local_bb1_ld__inst0_writedata[132] = gnd;

assign avm_local_bb1_ld__inst0_writedata[133] = gnd;

assign avm_local_bb1_ld__inst0_writedata[134] = gnd;

assign avm_local_bb1_ld__inst0_writedata[135] = gnd;

assign avm_local_bb1_ld__inst0_writedata[136] = gnd;

assign avm_local_bb1_ld__inst0_writedata[137] = gnd;

assign avm_local_bb1_ld__inst0_writedata[138] = gnd;

assign avm_local_bb1_ld__inst0_writedata[139] = gnd;

assign avm_local_bb1_ld__inst0_writedata[140] = gnd;

assign avm_local_bb1_ld__inst0_writedata[141] = gnd;

assign avm_local_bb1_ld__inst0_writedata[142] = gnd;

assign avm_local_bb1_ld__inst0_writedata[143] = gnd;

assign avm_local_bb1_ld__inst0_writedata[144] = gnd;

assign avm_local_bb1_ld__inst0_writedata[145] = gnd;

assign avm_local_bb1_ld__inst0_writedata[146] = gnd;

assign avm_local_bb1_ld__inst0_writedata[147] = gnd;

assign avm_local_bb1_ld__inst0_writedata[148] = gnd;

assign avm_local_bb1_ld__inst0_writedata[149] = gnd;

assign avm_local_bb1_ld__inst0_writedata[150] = gnd;

assign avm_local_bb1_ld__inst0_writedata[151] = gnd;

assign avm_local_bb1_ld__inst0_writedata[152] = gnd;

assign avm_local_bb1_ld__inst0_writedata[153] = gnd;

assign avm_local_bb1_ld__inst0_writedata[154] = gnd;

assign avm_local_bb1_ld__inst0_writedata[155] = gnd;

assign avm_local_bb1_ld__inst0_writedata[156] = gnd;

assign avm_local_bb1_ld__inst0_writedata[157] = gnd;

assign avm_local_bb1_ld__inst0_writedata[158] = gnd;

assign avm_local_bb1_ld__inst0_writedata[159] = gnd;

assign avm_local_bb1_ld__inst0_writedata[160] = gnd;

assign avm_local_bb1_ld__inst0_writedata[161] = gnd;

assign avm_local_bb1_ld__inst0_writedata[162] = gnd;

assign avm_local_bb1_ld__inst0_writedata[163] = gnd;

assign avm_local_bb1_ld__inst0_writedata[164] = gnd;

assign avm_local_bb1_ld__inst0_writedata[165] = gnd;

assign avm_local_bb1_ld__inst0_writedata[166] = gnd;

assign avm_local_bb1_ld__inst0_writedata[167] = gnd;

assign avm_local_bb1_ld__inst0_writedata[168] = gnd;

assign avm_local_bb1_ld__inst0_writedata[169] = gnd;

assign avm_local_bb1_ld__inst0_writedata[170] = gnd;

assign avm_local_bb1_ld__inst0_writedata[171] = gnd;

assign avm_local_bb1_ld__inst0_writedata[172] = gnd;

assign avm_local_bb1_ld__inst0_writedata[173] = gnd;

assign avm_local_bb1_ld__inst0_writedata[174] = gnd;

assign avm_local_bb1_ld__inst0_writedata[175] = gnd;

assign avm_local_bb1_ld__inst0_writedata[176] = gnd;

assign avm_local_bb1_ld__inst0_writedata[177] = gnd;

assign avm_local_bb1_ld__inst0_writedata[178] = gnd;

assign avm_local_bb1_ld__inst0_writedata[179] = gnd;

assign avm_local_bb1_ld__inst0_writedata[180] = gnd;

assign avm_local_bb1_ld__inst0_writedata[181] = gnd;

assign avm_local_bb1_ld__inst0_writedata[182] = gnd;

assign avm_local_bb1_ld__inst0_writedata[183] = gnd;

assign avm_local_bb1_ld__inst0_writedata[184] = gnd;

assign avm_local_bb1_ld__inst0_writedata[185] = gnd;

assign avm_local_bb1_ld__inst0_writedata[186] = gnd;

assign avm_local_bb1_ld__inst0_writedata[187] = gnd;

assign avm_local_bb1_ld__inst0_writedata[188] = gnd;

assign avm_local_bb1_ld__inst0_writedata[189] = gnd;

assign avm_local_bb1_ld__inst0_writedata[190] = gnd;

assign avm_local_bb1_ld__inst0_writedata[191] = gnd;

assign avm_local_bb1_ld__inst0_writedata[192] = gnd;

assign avm_local_bb1_ld__inst0_writedata[193] = gnd;

assign avm_local_bb1_ld__inst0_writedata[194] = gnd;

assign avm_local_bb1_ld__inst0_writedata[195] = gnd;

assign avm_local_bb1_ld__inst0_writedata[196] = gnd;

assign avm_local_bb1_ld__inst0_writedata[197] = gnd;

assign avm_local_bb1_ld__inst0_writedata[198] = gnd;

assign avm_local_bb1_ld__inst0_writedata[199] = gnd;

assign avm_local_bb1_ld__inst0_writedata[200] = gnd;

assign avm_local_bb1_ld__inst0_writedata[201] = gnd;

assign avm_local_bb1_ld__inst0_writedata[202] = gnd;

assign avm_local_bb1_ld__inst0_writedata[203] = gnd;

assign avm_local_bb1_ld__inst0_writedata[204] = gnd;

assign avm_local_bb1_ld__inst0_writedata[205] = gnd;

assign avm_local_bb1_ld__inst0_writedata[206] = gnd;

assign avm_local_bb1_ld__inst0_writedata[207] = gnd;

assign avm_local_bb1_ld__inst0_writedata[208] = gnd;

assign avm_local_bb1_ld__inst0_writedata[209] = gnd;

assign avm_local_bb1_ld__inst0_writedata[210] = gnd;

assign avm_local_bb1_ld__inst0_writedata[211] = gnd;

assign avm_local_bb1_ld__inst0_writedata[212] = gnd;

assign avm_local_bb1_ld__inst0_writedata[213] = gnd;

assign avm_local_bb1_ld__inst0_writedata[214] = gnd;

assign avm_local_bb1_ld__inst0_writedata[215] = gnd;

assign avm_local_bb1_ld__inst0_writedata[216] = gnd;

assign avm_local_bb1_ld__inst0_writedata[217] = gnd;

assign avm_local_bb1_ld__inst0_writedata[218] = gnd;

assign avm_local_bb1_ld__inst0_writedata[219] = gnd;

assign avm_local_bb1_ld__inst0_writedata[220] = gnd;

assign avm_local_bb1_ld__inst0_writedata[221] = gnd;

assign avm_local_bb1_ld__inst0_writedata[222] = gnd;

assign avm_local_bb1_ld__inst0_writedata[223] = gnd;

assign avm_local_bb1_ld__inst0_writedata[224] = gnd;

assign avm_local_bb1_ld__inst0_writedata[225] = gnd;

assign avm_local_bb1_ld__inst0_writedata[226] = gnd;

assign avm_local_bb1_ld__inst0_writedata[227] = gnd;

assign avm_local_bb1_ld__inst0_writedata[228] = gnd;

assign avm_local_bb1_ld__inst0_writedata[229] = gnd;

assign avm_local_bb1_ld__inst0_writedata[230] = gnd;

assign avm_local_bb1_ld__inst0_writedata[231] = gnd;

assign avm_local_bb1_ld__inst0_writedata[232] = gnd;

assign avm_local_bb1_ld__inst0_writedata[233] = gnd;

assign avm_local_bb1_ld__inst0_writedata[234] = gnd;

assign avm_local_bb1_ld__inst0_writedata[235] = gnd;

assign avm_local_bb1_ld__inst0_writedata[236] = gnd;

assign avm_local_bb1_ld__inst0_writedata[237] = gnd;

assign avm_local_bb1_ld__inst0_writedata[238] = gnd;

assign avm_local_bb1_ld__inst0_writedata[239] = gnd;

assign avm_local_bb1_ld__inst0_writedata[240] = gnd;

assign avm_local_bb1_ld__inst0_writedata[241] = gnd;

assign avm_local_bb1_ld__inst0_writedata[242] = gnd;

assign avm_local_bb1_ld__inst0_writedata[243] = gnd;

assign avm_local_bb1_ld__inst0_writedata[244] = gnd;

assign avm_local_bb1_ld__inst0_writedata[245] = gnd;

assign avm_local_bb1_ld__inst0_writedata[246] = gnd;

assign avm_local_bb1_ld__inst0_writedata[247] = gnd;

assign avm_local_bb1_ld__inst0_writedata[248] = gnd;

assign avm_local_bb1_ld__inst0_writedata[249] = gnd;

assign avm_local_bb1_ld__inst0_writedata[250] = gnd;

assign avm_local_bb1_ld__inst0_writedata[251] = gnd;

assign avm_local_bb1_ld__inst0_writedata[252] = gnd;

assign avm_local_bb1_ld__inst0_writedata[253] = gnd;

assign avm_local_bb1_ld__inst0_writedata[254] = gnd;

assign avm_local_bb1_ld__inst0_writedata[255] = gnd;

assign avm_local_bb1_ld__inst0_byteenable[0] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[1] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[2] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[3] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[4] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[5] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[6] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[7] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[8] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[9] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[10] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[11] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[12] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[13] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[14] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[15] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[16] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[17] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[18] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[19] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[20] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[21] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[22] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[23] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[24] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[25] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[26] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[27] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[28] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[29] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[30] = vcc;

assign avm_local_bb1_ld__inst0_byteenable[31] = vcc;

assign avm_local_bb1_ld__inst0_burstcount[0] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] ;

assign avm_local_bb1_ld__inst0_burstcount[1] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] ;

assign avm_local_bb1_ld__inst0_burstcount[2] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] ;

assign avm_local_bb1_ld__inst0_burstcount[3] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] ;

assign avm_local_bb1_ld__inst0_burstcount[4] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] ;

assign avm_local_bb1_ld__u0_inst0_enable = vcc;

assign avm_local_bb1_ld__u0_inst0_address[0] = gnd;

assign avm_local_bb1_ld__u0_inst0_address[1] = gnd;

assign avm_local_bb1_ld__u0_inst0_address[2] = gnd;

assign avm_local_bb1_ld__u0_inst0_address[3] = gnd;

assign avm_local_bb1_ld__u0_inst0_address[4] = gnd;

assign avm_local_bb1_ld__u0_inst0_address[5] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] ;

assign avm_local_bb1_ld__u0_inst0_address[6] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] ;

assign avm_local_bb1_ld__u0_inst0_address[7] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] ;

assign avm_local_bb1_ld__u0_inst0_address[8] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] ;

assign avm_local_bb1_ld__u0_inst0_address[9] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] ;

assign avm_local_bb1_ld__u0_inst0_address[10] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] ;

assign avm_local_bb1_ld__u0_inst0_address[11] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] ;

assign avm_local_bb1_ld__u0_inst0_address[12] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] ;

assign avm_local_bb1_ld__u0_inst0_address[13] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] ;

assign avm_local_bb1_ld__u0_inst0_address[14] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] ;

assign avm_local_bb1_ld__u0_inst0_address[15] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] ;

assign avm_local_bb1_ld__u0_inst0_address[16] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] ;

assign avm_local_bb1_ld__u0_inst0_address[17] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] ;

assign avm_local_bb1_ld__u0_inst0_address[18] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] ;

assign avm_local_bb1_ld__u0_inst0_address[19] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] ;

assign avm_local_bb1_ld__u0_inst0_address[20] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] ;

assign avm_local_bb1_ld__u0_inst0_address[21] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] ;

assign avm_local_bb1_ld__u0_inst0_address[22] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] ;

assign avm_local_bb1_ld__u0_inst0_address[23] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] ;

assign avm_local_bb1_ld__u0_inst0_address[24] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] ;

assign avm_local_bb1_ld__u0_inst0_address[25] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] ;

assign avm_local_bb1_ld__u0_inst0_address[26] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] ;

assign avm_local_bb1_ld__u0_inst0_address[27] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] ;

assign avm_local_bb1_ld__u0_inst0_address[28] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] ;

assign avm_local_bb1_ld__u0_inst0_address[29] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] ;

assign avm_local_bb1_ld__u0_inst0_address[30] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] ;

assign avm_local_bb1_ld__u0_inst0_read = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ;

assign avm_local_bb1_ld__u0_inst0_write = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[0] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[1] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[2] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[3] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[4] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[5] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[6] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[7] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[8] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[9] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[10] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[11] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[12] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[13] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[14] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[15] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[16] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[17] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[18] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[19] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[20] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[21] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[22] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[23] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[24] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[25] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[26] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[27] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[28] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[29] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[30] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[31] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[32] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[33] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[34] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[35] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[36] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[37] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[38] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[39] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[40] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[41] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[42] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[43] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[44] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[45] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[46] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[47] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[48] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[49] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[50] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[51] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[52] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[53] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[54] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[55] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[56] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[57] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[58] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[59] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[60] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[61] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[62] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[63] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[64] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[65] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[66] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[67] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[68] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[69] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[70] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[71] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[72] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[73] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[74] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[75] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[76] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[77] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[78] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[79] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[80] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[81] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[82] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[83] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[84] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[85] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[86] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[87] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[88] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[89] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[90] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[91] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[92] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[93] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[94] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[95] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[96] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[97] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[98] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[99] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[100] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[101] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[102] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[103] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[104] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[105] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[106] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[107] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[108] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[109] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[110] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[111] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[112] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[113] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[114] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[115] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[116] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[117] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[118] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[119] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[120] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[121] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[122] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[123] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[124] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[125] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[126] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[127] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[128] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[129] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[130] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[131] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[132] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[133] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[134] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[135] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[136] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[137] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[138] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[139] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[140] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[141] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[142] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[143] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[144] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[145] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[146] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[147] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[148] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[149] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[150] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[151] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[152] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[153] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[154] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[155] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[156] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[157] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[158] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[159] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[160] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[161] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[162] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[163] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[164] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[165] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[166] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[167] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[168] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[169] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[170] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[171] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[172] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[173] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[174] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[175] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[176] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[177] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[178] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[179] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[180] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[181] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[182] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[183] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[184] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[185] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[186] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[187] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[188] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[189] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[190] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[191] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[192] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[193] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[194] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[195] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[196] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[197] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[198] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[199] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[200] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[201] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[202] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[203] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[204] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[205] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[206] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[207] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[208] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[209] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[210] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[211] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[212] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[213] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[214] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[215] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[216] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[217] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[218] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[219] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[220] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[221] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[222] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[223] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[224] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[225] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[226] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[227] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[228] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[229] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[230] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[231] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[232] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[233] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[234] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[235] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[236] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[237] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[238] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[239] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[240] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[241] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[242] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[243] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[244] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[245] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[246] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[247] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[248] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[249] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[250] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[251] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[252] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[253] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[254] = gnd;

assign avm_local_bb1_ld__u0_inst0_writedata[255] = gnd;

assign avm_local_bb1_ld__u0_inst0_byteenable[0] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[1] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[2] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[3] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[4] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[5] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[6] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[7] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[8] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[9] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[10] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[11] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[12] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[13] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[14] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[15] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[16] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[17] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[18] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[19] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[20] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[21] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[22] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[23] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[24] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[25] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[26] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[27] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[28] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[29] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[30] = vcc;

assign avm_local_bb1_ld__u0_inst0_byteenable[31] = vcc;

assign avm_local_bb1_ld__u0_inst0_burstcount[0] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] ;

assign avm_local_bb1_ld__u0_inst0_burstcount[1] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] ;

assign avm_local_bb1_ld__u0_inst0_burstcount[2] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] ;

assign avm_local_bb1_ld__u0_inst0_burstcount[3] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] ;

assign avm_local_bb1_ld__u0_inst0_burstcount[4] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] ;

assign avm_local_bb1_st_c0_exe1_inst0_enable = vcc;

assign avm_local_bb1_st_c0_exe1_inst0_address[0] = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_address[1] = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_address[2] = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_address[3] = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_address[4] = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_address[5] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[6] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[7] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[8] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[9] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[10] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[11] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[12] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[13] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[14] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[15] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[16] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[17] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[18] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[19] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[20] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[21] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[22] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[23] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[24] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[25] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[26] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[27] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[28] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[29] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24 ;

assign avm_local_bb1_st_c0_exe1_inst0_address[30] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25 ;

assign avm_local_bb1_st_c0_exe1_inst0_read = gnd;

assign avm_local_bb1_st_c0_exe1_inst0_write = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[0] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[1] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[2] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[3] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[4] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[5] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[6] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[7] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[8] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[9] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[10] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[11] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[12] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[13] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[14] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[15] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[16] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[17] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[18] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[19] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[20] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[21] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[22] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[23] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[24] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[25] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[26] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[27] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[28] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[29] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[30] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[31] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[32] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[33] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[34] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[35] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[36] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[37] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[38] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[39] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[40] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[41] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[42] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[43] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[44] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[45] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[46] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[47] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[48] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[49] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[50] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[51] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[52] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[53] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[54] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[55] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[56] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[57] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[58] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[59] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[60] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[61] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[62] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[63] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[64] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[65] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[66] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[67] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[68] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[69] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[70] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[71] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[72] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[73] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[74] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[75] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[76] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[77] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[78] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[79] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[80] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[81] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[82] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[83] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[84] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[85] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[86] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[87] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[88] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[89] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[90] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[91] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[92] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[93] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[94] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[95] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[96] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[97] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[98] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[99] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[100] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[101] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[102] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[103] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[104] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[105] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[106] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[107] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[108] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[109] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[110] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[111] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[112] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[113] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[114] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[115] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[116] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[117] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[118] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[119] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[120] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[121] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[122] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[123] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[124] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[125] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[126] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[127] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[128] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[129] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[130] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[131] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[132] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[133] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[134] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[135] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[136] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[137] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[138] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[139] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[140] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[141] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[142] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[143] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[144] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[145] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[146] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[147] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[148] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[149] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[150] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[151] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[152] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[153] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[154] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[155] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[156] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[157] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[158] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[159] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[160] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[192]~160 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[161] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[193]~161 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[162] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[194]~162 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[163] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[195]~163 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[164] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[196]~164 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[165] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[197]~165 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[166] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[198]~166 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[167] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[199]~167 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[168] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[200]~168 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[169] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[201]~169 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[170] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[202]~170 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[171] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[203]~171 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[172] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[204]~172 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[173] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[205]~173 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[174] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[206]~174 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[175] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[207]~175 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[176] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[208]~176 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[177] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[209]~177 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[178] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[210]~178 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[179] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[211]~179 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[180] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[212]~180 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[181] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[213]~181 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[182] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[214]~182 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[183] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[215]~183 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[184] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[216]~184 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[185] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[217]~185 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[186] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[218]~186 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[187] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[219]~187 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[188] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[220]~188 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[189] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[221]~189 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[190] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[222]~190 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[191] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[223]~191 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[192] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[224]~192 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[193] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[225]~193 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[194] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[226]~194 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[195] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[227]~195 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[196] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[228]~196 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[197] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[229]~197 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[198] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[230]~198 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[199] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[231]~199 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[200] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[232]~200 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[201] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[233]~201 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[202] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[234]~202 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[203] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[235]~203 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[204] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[236]~204 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[205] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[237]~205 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[206] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[238]~206 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[207] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[239]~207 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[208] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[240]~208 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[209] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[241]~209 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[210] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[242]~210 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[211] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[243]~211 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[212] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[244]~212 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[213] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[245]~213 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[214] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[246]~214 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[215] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[247]~215 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[216] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[248]~216 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[217] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[249]~217 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[218] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[250]~218 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[219] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[251]~219 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[220] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[252]~220 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[221] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[253]~221 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[222] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[254]~222 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[223] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[255]~223 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[224] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[256]~224 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[225] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[257]~225 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[226] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[258]~226 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[227] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[259]~227 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[228] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[260]~228 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[229] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[261]~229 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[230] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[262]~230 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[231] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[263]~231 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[232] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[264]~232 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[233] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[265]~233 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[234] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[266]~234 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[235] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[267]~235 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[236] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[268]~236 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[237] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[269]~237 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[238] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[270]~238 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[239] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[271]~239 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[240] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[272]~240 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[241] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[273]~241 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[242] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[274]~242 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[243] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[275]~243 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[244] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[276]~244 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[245] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[277]~245 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[246] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[278]~246 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[247] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[279]~247 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[248] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[280]~248 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[249] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[281]~249 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[250] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[282]~250 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[251] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[283]~251 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[252] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[284]~252 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[253] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[285]~253 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[254] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[286]~254 ;

assign avm_local_bb1_st_c0_exe1_inst0_writedata[255] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[287]~255 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[0] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~256 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[1] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~257 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[2] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~258 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[3] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~259 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[4] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~260 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[5] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~261 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[6] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~262 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[7] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~263 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[8] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~264 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[9] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~265 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[10] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~266 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[11] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~267 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[12] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~268 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[13] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~269 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[14] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~270 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[15] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~271 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[16] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~272 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[17] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~273 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[18] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~274 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[19] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~275 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[20] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~276 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[21] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~277 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[22] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~278 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[23] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~279 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[24] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~280 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[25] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~281 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[26] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~282 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[27] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~283 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[28] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~284 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[29] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~285 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[30] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~286 ;

assign avm_local_bb1_st_c0_exe1_inst0_byteenable[31] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[31]~287 ;

assign avm_local_bb1_st_c0_exe1_inst0_burstcount[0] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26 ;

assign avm_local_bb1_st_c0_exe1_inst0_burstcount[1] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27 ;

assign avm_local_bb1_st_c0_exe1_inst0_burstcount[2] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28 ;

assign avm_local_bb1_st_c0_exe1_inst0_burstcount[3] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29 ;

assign avm_local_bb1_st_c0_exe1_inst0_burstcount[4] = \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30 ;

assign \clock~input0  = clock;

cyclonev_clkena \clock~CLKENA0_I (
	.inclk(\clock~input0 ),
	.outclk(\clock~CLKENA0 ));
defparam \clock~CLKENA0_I .clock_type = "Global Clock";
defparam \clock~CLKENA0_I .ena_register_mode = "always enabled";
defparam \clock~CLKENA0_I .ena_register_power_up = "high";
defparam \clock~CLKENA0_I .disable_mode = "low";
defparam \clock~CLKENA0_I .test_syn = "high";

assign \avs_cra_address[1]~input0  = avs_cra_address[1];

assign \avs_cra_address[2]~input0  = avs_cra_address[2];

assign \avs_cra_address[0]~input0  = avs_cra_address[0];

assign \avs_cra_address[3]~input0  = avs_cra_address[3];

cyclonev_lcell_comb \WideOr1~0_I (
	.datab(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[3]~input0 ),
	.combout(\WideOr1~0 ));
defparam \WideOr1~0_I .shared_arith = "off";
defparam \WideOr1~0_I .extended_lut = "off";
defparam \WideOr1~0_I .lut_mask = "C3C3CFCFFFFFFFFF";

assign \avs_cra_write~input0  = avs_cra_write;

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder_I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF";

assign \resetn~input0  = resetn;

cyclonev_clkena \resetn~CLKENA0_I (
	.inclk(\resetn~input0 ),
	.outclk(\resetn~CLKENA0 ));
defparam \resetn~CLKENA0_I .clock_type = "Global Clock";
defparam \resetn~CLKENA0_I .ena_register_mode = "always enabled";
defparam \resetn~CLKENA0_I .ena_register_power_up = "high";
defparam \resetn~CLKENA0_I .disable_mode = "low";
defparam \resetn~CLKENA0_I .test_syn = "high";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2_I .lut_mask = "FF00FF0000000000";

assign \avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0  = avm_local_bb1_st_c0_exe1_inst0_waitrequest;

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "5A5A5A5A55555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__empty_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|write~0_I .lut_mask = "5555555544444444";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0_I .lut_mask = "00000000AAAAFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready~I .lut_mask = "0F0F0000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder_I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__inputs_ready ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid~I .lut_mask = "00CC00CC00CC00CC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(local_bb1_ld__valid_out_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__combined_valid~I .lut_mask = "55555555FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__stall_in ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_combined_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready~I .lut_mask = "FFFFFFFFFFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .lut_mask = "0000000000550055";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder_I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder_I .lut_mask = "FFFFFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE_I .created_from = "Q(empty_dff)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .lut_mask = "0000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .lut_mask = "0000000000400000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .lut_mask = "5AFF5AFF50F550F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .lut_mask = "4FDF4FDF0F9F0F9F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .lut_mask = "00000000FAFAFAFA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .lut_mask = "0F0F0F0F0FF00FF0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .lut_mask = "0000000000000002";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .lut_mask = "0010FFFF0000FDFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|R_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .lut_mask = "FFAAFFAAFFAAFFAA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_inputs_ready ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0_I .lut_mask = "3333000033330000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0_I .lut_mask = "00000000CCCCFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready~I .lut_mask = "5050FFFF5050FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_inputs_ready ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid~I .lut_mask = "00000000F0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_stall_in_0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors~I .lut_mask = "C8C8C800FAFAFA00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__always1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0_I .lut_mask = "F0F0F0F000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_0_staging_reg_NO_SHIFT_REG~I .is_wysiwyg = "true";

assign \avm_local_bb1_st_c0_exe1_inst0_writeack~input0  = avm_local_bb1_st_c0_exe1_inst0_writeack;

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "55555555AAAA5555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "0FFF0FFF0A5F0A5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I (
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .lut_mask = "0000CCCCCCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3_I .lut_mask = "5AFF5AFF50F550F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "46DF46DF029B029B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~0_I .lut_mask = "FFF0FFF000F000F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[1] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~1_I .lut_mask = "000300030F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2_I .lut_mask = "05050505FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~DUPLICATE_I .created_from = "Q(valid)";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3_I .lut_mask = "3CFF3CFF30F330F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "11DD11DDC0F3C0F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .created_from = "Q(wrreq_delaya[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~0_I .lut_mask = "F5F5F5F5A0A0A0A0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~1_I .lut_mask = "00000000333F333F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2_I .lut_mask = "00FF00FF0FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5_I .lut_mask = "55FF55FFA0F5A0F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "46DF46DF029B029B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .created_from = "Q(wrreq_delaya[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~0_I .lut_mask = "CFCFCFCFC0C0C0C0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~DUPLICATE ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~1_I .lut_mask = "1111111115151515";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2_I .lut_mask = "00FF30FF00FF33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FFFF0000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "0000FFFFCCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9_I .lut_mask = "3070303030703070";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00CC00CC33FF33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00FF00FF0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "0000CCCC3333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00F000F00FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|low_addressa[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__pulse_ram_output~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__low_addressa[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8_I .lut_mask = "0000CCCC3333FFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups ));
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~COUT ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0_I (
	.datac(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0_I .lut_mask = "0F0F0F0FFFFFFFFF";

assign \avs_cra_writedata[13]~input0  = avs_cra_writedata[13];

assign \avs_cra_byteenable[1]~input0  = avs_cra_byteenable[1];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][8]~6_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_write~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][8]~6 ));
defparam \local_size_NO_SHIFT_REG[0][8]~6_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][8]~6_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][8]~6_I .lut_mask = "0000000000020000";

dffeas \local_size_NO_SHIFT_REG[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][13] ));
defparam \local_size_NO_SHIFT_REG[0][13]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][13]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[12]~input0  = avs_cra_writedata[12];

dffeas \local_size_NO_SHIFT_REG[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[12]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][12] ));
defparam \local_size_NO_SHIFT_REG[0][12]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][12]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[11]~input0  = avs_cra_writedata[11];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[11]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][11]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][11]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][11]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][11] ));
defparam \local_size_NO_SHIFT_REG[0][11]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][11]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[10]~input0  = avs_cra_writedata[10];

dffeas \local_size_NO_SHIFT_REG[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][10] ));
defparam \local_size_NO_SHIFT_REG[0][10]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][10]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[9]~input0  = avs_cra_writedata[9];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][9]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[9]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][9]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][9]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][9]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][9]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][9] ));
defparam \local_size_NO_SHIFT_REG[0][9]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][9]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[8]~input0  = avs_cra_writedata[8];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[8]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][8]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][8]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][8]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][8] ));
defparam \local_size_NO_SHIFT_REG[0][8]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][8]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[7]~input0  = avs_cra_writedata[7];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][7]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[7]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][7]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][7]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][7]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

assign \avs_cra_byteenable[0]~input0  = avs_cra_byteenable[0];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][0]~1_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][0]~1 ));
defparam \local_size_NO_SHIFT_REG[0][0]~1_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][0]~1_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][0]~1_I .lut_mask = "0001000000000000";

dffeas \local_size_NO_SHIFT_REG[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][7] ));
defparam \local_size_NO_SHIFT_REG[0][7]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][7]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[6]~input0  = avs_cra_writedata[6];

dffeas \local_size_NO_SHIFT_REG[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[6]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][6] ));
defparam \local_size_NO_SHIFT_REG[0][6]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][6]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[5]~input0  = avs_cra_writedata[5];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[5]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][5]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][5]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][5]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][5] ));
defparam \local_size_NO_SHIFT_REG[0][5]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][5]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[4]~input0  = avs_cra_writedata[4];

dffeas \local_size_NO_SHIFT_REG[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[4]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][4] ));
defparam \local_size_NO_SHIFT_REG[0][4]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][4]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[3]~input0  = avs_cra_writedata[3];

dffeas \local_size_NO_SHIFT_REG[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[3]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][3] ));
defparam \local_size_NO_SHIFT_REG[0][3]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][3]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[2]~input0  = avs_cra_writedata[2];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][2]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][2]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][2]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][2]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][2]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][2] ));
defparam \local_size_NO_SHIFT_REG[0][2]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][2]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[1]~input0  = avs_cra_writedata[1];

dffeas \local_size_NO_SHIFT_REG[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[1]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][1] ));
defparam \local_size_NO_SHIFT_REG[0][1]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][1]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[0]~input0  = avs_cra_writedata[0];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][0]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[0]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][0]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][0]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][0]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][0]~1 ),
	.q(\local_size_NO_SHIFT_REG[0][0] ));
defparam \local_size_NO_SHIFT_REG[0][0]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][0] ),
	.cin(gnd),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[13]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[12]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[11]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[9]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[13] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[12] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[11] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[9] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[10] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~1_I .lut_mask = "8800000000000000";

assign \avs_cra_writedata[31]~input0  = avs_cra_writedata[31];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][31]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[31]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][31]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][31]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][31]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][31]~feeder_I .lut_mask = "00000000FFFFFFFF";

assign \avs_cra_byteenable[3]~input0  = avs_cra_byteenable[3];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][24]~8_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][24]~8 ));
defparam \local_size_NO_SHIFT_REG[0][24]~8_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][24]~8_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][24]~8_I .lut_mask = "0000010000000000";

dffeas \local_size_NO_SHIFT_REG[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][31]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][31] ));
defparam \local_size_NO_SHIFT_REG[0][31]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][31]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[30]~input0  = avs_cra_writedata[30];

dffeas \local_size_NO_SHIFT_REG[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[30]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][30] ));
defparam \local_size_NO_SHIFT_REG[0][30]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][30]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[29]~input0  = avs_cra_writedata[29];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[29]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][29]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][29]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][29]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][29] ));
defparam \local_size_NO_SHIFT_REG[0][29]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][29]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[28]~input0  = avs_cra_writedata[28];

dffeas \local_size_NO_SHIFT_REG[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[28]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][28] ));
defparam \local_size_NO_SHIFT_REG[0][28]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][28]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[27]~input0  = avs_cra_writedata[27];

dffeas \local_size_NO_SHIFT_REG[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[27]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][27] ));
defparam \local_size_NO_SHIFT_REG[0][27]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][27]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[26]~input0  = avs_cra_writedata[26];

dffeas \local_size_NO_SHIFT_REG[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[26]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][26] ));
defparam \local_size_NO_SHIFT_REG[0][26]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][26]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[25]~input0  = avs_cra_writedata[25];

dffeas \local_size_NO_SHIFT_REG[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[25]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][25] ));
defparam \local_size_NO_SHIFT_REG[0][25]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][25]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[24]~input0  = avs_cra_writedata[24];

dffeas \local_size_NO_SHIFT_REG[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[24]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][24]~8 ),
	.q(\local_size_NO_SHIFT_REG[0][24] ));
defparam \local_size_NO_SHIFT_REG[0][24]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][24]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[23]~input0  = avs_cra_writedata[23];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][23]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[23]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][23]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][23]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][23]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF";

assign \avs_cra_byteenable[2]~input0  = avs_cra_byteenable[2];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][16]~7_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][16]~7 ));
defparam \local_size_NO_SHIFT_REG[0][16]~7_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][16]~7_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][16]~7_I .lut_mask = "0000000001000000";

dffeas \local_size_NO_SHIFT_REG[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][23]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][23] ));
defparam \local_size_NO_SHIFT_REG[0][23]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][23]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[22]~input0  = avs_cra_writedata[22];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][22]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[22]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][22]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][22]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][22]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][22] ));
defparam \local_size_NO_SHIFT_REG[0][22]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][22]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[21]~input0  = avs_cra_writedata[21];

dffeas \local_size_NO_SHIFT_REG[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[21]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][21] ));
defparam \local_size_NO_SHIFT_REG[0][21]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][21]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[20]~input0  = avs_cra_writedata[20];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[20]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][20]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][20]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][20]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][20] ));
defparam \local_size_NO_SHIFT_REG[0][20]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][20]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[19]~input0  = avs_cra_writedata[19];

dffeas \local_size_NO_SHIFT_REG[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[19]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][19] ));
defparam \local_size_NO_SHIFT_REG[0][19]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][19]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[18]~input0  = avs_cra_writedata[18];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[18]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][18]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][18]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][18]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][18] ));
defparam \local_size_NO_SHIFT_REG[0][18]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][18]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[17]~input0  = avs_cra_writedata[17];

dffeas \local_size_NO_SHIFT_REG[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][17] ));
defparam \local_size_NO_SHIFT_REG[0][17]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][17]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[16]~input0  = avs_cra_writedata[16];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][16]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[16]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][16]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][16]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][16]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][16]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][16]~7 ),
	.q(\local_size_NO_SHIFT_REG[0][16] ));
defparam \local_size_NO_SHIFT_REG[0][16]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][16]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[15]~input0  = avs_cra_writedata[15];

dffeas \local_size_NO_SHIFT_REG[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[15]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][15] ));
defparam \local_size_NO_SHIFT_REG[0][15]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][15]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[14]~input0  = avs_cra_writedata[14];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[0][14]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[14]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[0][14]~feeder ));
defparam \local_size_NO_SHIFT_REG[0][14]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[0][14]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[0][14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[0][14]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[0][8]~6 ),
	.q(\local_size_NO_SHIFT_REG[0][14] ));
defparam \local_size_NO_SHIFT_REG[0][14]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~78 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~78 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][31] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73_I .lut_mask = "0000000000005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[31]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[30]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~DUPLICATE_I .created_from = "Q(max_local_id_0[29])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~DUPLICATE_I .created_from = "Q(max_local_id_0[28])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[30] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~3_I .lut_mask = "8000800000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[17]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[16]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[19]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[17] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[16] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[19] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[15] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~2_I .lut_mask = "8080000000000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0_I (
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[0][0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~DUPLICATE_I .created_from = "Q(max_local_id_0[0])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[14]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[26]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[8]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[1]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~DUPLICATE_I .created_from = "Q(max_local_id_0[20])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[14] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[26] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[8] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[1] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~6_I .lut_mask = "8000000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[3]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[4]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[5]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[6]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[7] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[3] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[4] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[5] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[6] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[2] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~0_I .lut_mask = "8000000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~DUPLICATE_I .created_from = "Q(max_local_id_0[25])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[23]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[24]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~DUPLICATE_I .created_from = "Q(max_local_id_0[22])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25]~DUPLICATE ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[23] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[24] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~4_I .lut_mask = "C000000000000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~1 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~3 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~2 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~6 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~4 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal3~5_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1_I (
	.datac(__ALT_INV__start_NO_SHIFT_REG),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~5 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1_I .lut_mask = "0F0FFFFF0F0F0F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~DUPLICATE_I .created_from = "Q(local_id_0[1])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~DUPLICATE_I .created_from = "Q(local_id_0[6])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[6]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~DUPLICATE_I .created_from = "Q(local_id_0[8])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[7] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[8] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[6] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[6] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[7] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[8]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~3_I .lut_mask = "8008400420021001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[13] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[14] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[13] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[12] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[14] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[12] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~1_I .lut_mask = "8400210000840021";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[17]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[15]~DUPLICATE_I .created_from = "Q(local_id_0[15])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[16] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[17] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[17] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[15] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[15]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[16] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~0_I .lut_mask = "8200008241000041";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[1]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[1] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[2] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[0] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[2] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[1] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~4_I .lut_mask = "8020080240100401";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[11] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[11] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[10] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[10] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[9] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[9] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~2_I .lut_mask = "9009000000009009";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[3]~DUPLICATE_I .created_from = "Q(local_id_0[3])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[4] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[5] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[4] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[3] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[3]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[5] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~5_I .lut_mask = "8400008421000021";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~3 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~1 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~0 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~4 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~2 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~5 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~DUPLICATE_I .created_from = "Q(local_id_0[26])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~74 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[31] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~74 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[30] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[31] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[30] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~7_I .lut_mask = "8484848421212121";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[28]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[29]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[27]~DUPLICATE_I .created_from = "Q(max_local_id_0[27])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[27] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[29] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[29] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[28] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~8_I .lut_mask = "8008400420021001";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[21]~DUPLICATE_I .created_from = "Q(max_local_id_0[21])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[23] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[21] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[22] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[23] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~11_I .lut_mask = "8400008421000021";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add3~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[8]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_0[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[26] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25]~DUPLICATE ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[26] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[24] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[25] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[24] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~9_I .lut_mask = "8400210000840021";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[18]~DUPLICATE_I .created_from = "Q(max_local_id_0[18])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[19] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[20] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_0[18] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[19] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~10_I .lut_mask = "8008400420021001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~7 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~8 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~11 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~9 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~10 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~12_I .lut_mask = "0000000000000101";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~6 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~12 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal0~13_I .lut_mask = "000000000F0F0F0F";

assign \avs_cra_writedata[32]~input0  = avs_cra_writedata[32];

assign \avs_cra_byteenable[4]~input0  = avs_cra_byteenable[4];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][0]~2_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[4]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][0]~2 ));
defparam \local_size_NO_SHIFT_REG[1][0]~2_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][0]~2_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][0]~2_I .lut_mask = "0000000200000000";

dffeas \local_size_NO_SHIFT_REG[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[32]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][0] ));
defparam \local_size_NO_SHIFT_REG[1][0]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0_I (
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[1][0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[0]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[34]~input0  = avs_cra_writedata[34];

dffeas \local_size_NO_SHIFT_REG[1][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[34]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][2] ));
defparam \local_size_NO_SHIFT_REG[1][2]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][2]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[33]~input0  = avs_cra_writedata[33];

dffeas \local_size_NO_SHIFT_REG[1][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[33]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][1] ));
defparam \local_size_NO_SHIFT_REG[1][1]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][0] ),
	.cin(gnd),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[2]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[44]~input0  = avs_cra_writedata[44];

assign \avs_cra_byteenable[5]~input0  = avs_cra_byteenable[5];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][8]~9_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[5]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][8]~9 ));
defparam \local_size_NO_SHIFT_REG[1][8]~9_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][8]~9_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][8]~9_I .lut_mask = "0000000200000000";

dffeas \local_size_NO_SHIFT_REG[1][12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[44]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][12] ));
defparam \local_size_NO_SHIFT_REG[1][12]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][12]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[43]~input0  = avs_cra_writedata[43];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[43]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][11]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][11]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][11]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][11] ));
defparam \local_size_NO_SHIFT_REG[1][11]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][11]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[42]~input0  = avs_cra_writedata[42];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][10]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[42]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][10]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][10]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][10]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][10]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][10] ));
defparam \local_size_NO_SHIFT_REG[1][10]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][10]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[41]~input0  = avs_cra_writedata[41];

dffeas \local_size_NO_SHIFT_REG[1][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[41]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][9] ));
defparam \local_size_NO_SHIFT_REG[1][9]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][9]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[40]~input0  = avs_cra_writedata[40];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[40]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][8]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][8]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][8]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][8] ));
defparam \local_size_NO_SHIFT_REG[1][8]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][8]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[39]~input0  = avs_cra_writedata[39];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][7]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[39]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][7]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][7]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][7]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][7] ));
defparam \local_size_NO_SHIFT_REG[1][7]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][7]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[38]~input0  = avs_cra_writedata[38];

dffeas \local_size_NO_SHIFT_REG[1][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[38]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][6] ));
defparam \local_size_NO_SHIFT_REG[1][6]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][6]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[37]~input0  = avs_cra_writedata[37];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[37]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][5]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][5]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][5]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][5] ));
defparam \local_size_NO_SHIFT_REG[1][5]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][5]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[36]~input0  = avs_cra_writedata[36];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[36]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][4]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][4]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][4]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][4] ));
defparam \local_size_NO_SHIFT_REG[1][4]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][4]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[35]~input0  = avs_cra_writedata[35];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][3]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[35]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][3]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][3]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][3]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][0]~2 ),
	.q(\local_size_NO_SHIFT_REG[1][3] ));
defparam \local_size_NO_SHIFT_REG[1][3]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[1][3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[1][4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[1][5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[1][11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[1][12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13_I .lut_mask = "00000000000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[12]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[11]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[45]~input0  = avs_cra_writedata[45];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][13]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[45]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][13]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][13]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][13]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][13]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][13] ));
defparam \local_size_NO_SHIFT_REG[1][13]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[13]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[10]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[12] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[11] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[13] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[10] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[9] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~2_I .lut_mask = "8000800000000000";

assign \avs_cra_writedata[53]~input0  = avs_cra_writedata[53];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][21]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[53]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][21]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][21]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][21]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][21]~feeder_I .lut_mask = "00000000FFFFFFFF";

assign \avs_cra_byteenable[6]~input0  = avs_cra_byteenable[6];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][16]~10_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[6]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][16]~10 ));
defparam \local_size_NO_SHIFT_REG[1][16]~10_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][16]~10_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][16]~10_I .lut_mask = "0000001000000000";

dffeas \local_size_NO_SHIFT_REG[1][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][21]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][21] ));
defparam \local_size_NO_SHIFT_REG[1][21]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][21]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[52]~input0  = avs_cra_writedata[52];

dffeas \local_size_NO_SHIFT_REG[1][20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[52]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][20] ));
defparam \local_size_NO_SHIFT_REG[1][20]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][20]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[51]~input0  = avs_cra_writedata[51];

dffeas \local_size_NO_SHIFT_REG[1][19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[51]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][19] ));
defparam \local_size_NO_SHIFT_REG[1][19]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][19]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[50]~input0  = avs_cra_writedata[50];

dffeas \local_size_NO_SHIFT_REG[1][18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[50]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][18] ));
defparam \local_size_NO_SHIFT_REG[1][18]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][18]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[49]~input0  = avs_cra_writedata[49];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][17]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[49]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][17]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][17]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][17]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][17]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][17] ));
defparam \local_size_NO_SHIFT_REG[1][17]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][17]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[48]~input0  = avs_cra_writedata[48];

dffeas \local_size_NO_SHIFT_REG[1][16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[48]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][16] ));
defparam \local_size_NO_SHIFT_REG[1][16]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][16]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[47]~input0  = avs_cra_writedata[47];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][15]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[47]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][15]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][15]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][15]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][15]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][15] ));
defparam \local_size_NO_SHIFT_REG[1][15]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][15]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[46]~input0  = avs_cra_writedata[46];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][14]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[46]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][14]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][14]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][14]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][14]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][8]~9 ),
	.q(\local_size_NO_SHIFT_REG[1][14] ));
defparam \local_size_NO_SHIFT_REG[1][14]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[1][17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[21]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[63]~input0  = avs_cra_writedata[63];

assign \avs_cra_byteenable[7]~input0  = avs_cra_byteenable[7];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][24]~11_I (
	.dataa(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[7]~input0 ),
	.dataf(\__ALT_INV__avs_cra_write~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][24]~11 ));
defparam \local_size_NO_SHIFT_REG[1][24]~11_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][24]~11_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][24]~11_I .lut_mask = "0000000000000008";

dffeas \local_size_NO_SHIFT_REG[1][31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[63]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][31] ));
defparam \local_size_NO_SHIFT_REG[1][31]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][31]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[62]~input0  = avs_cra_writedata[62];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[62]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][30]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][30]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][30]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][30] ));
defparam \local_size_NO_SHIFT_REG[1][30]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][30]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[61]~input0  = avs_cra_writedata[61];

dffeas \local_size_NO_SHIFT_REG[1][29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[61]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][29] ));
defparam \local_size_NO_SHIFT_REG[1][29]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][29]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[60]~input0  = avs_cra_writedata[60];

dffeas \local_size_NO_SHIFT_REG[1][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[60]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][28] ));
defparam \local_size_NO_SHIFT_REG[1][28]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][28]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[59]~input0  = avs_cra_writedata[59];

dffeas \local_size_NO_SHIFT_REG[1][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[59]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][27] ));
defparam \local_size_NO_SHIFT_REG[1][27]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][27]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[58]~input0  = avs_cra_writedata[58];

dffeas \local_size_NO_SHIFT_REG[1][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[58]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][26] ));
defparam \local_size_NO_SHIFT_REG[1][26]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][26]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[57]~input0  = avs_cra_writedata[57];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[57]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][25]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][25]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][25]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[1][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][25] ));
defparam \local_size_NO_SHIFT_REG[1][25]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][25]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[56]~input0  = avs_cra_writedata[56];

dffeas \local_size_NO_SHIFT_REG[1][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[56]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[1][24]~11 ),
	.q(\local_size_NO_SHIFT_REG[1][24] ));
defparam \local_size_NO_SHIFT_REG[1][24]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][24]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[55]~input0  = avs_cra_writedata[55];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][23]~feeder_I (
	.datab(\__ALT_INV__avs_cra_writedata[55]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][23]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][23]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][23]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][23]~feeder_I .lut_mask = "3333333333333333";

dffeas \local_size_NO_SHIFT_REG[1][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][23]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][23] ));
defparam \local_size_NO_SHIFT_REG[1][23]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][23]~I .is_wysiwyg = "true";

assign \avs_cra_writedata[54]~input0  = avs_cra_writedata[54];

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[1][22]~feeder_I (
	.datab(\__ALT_INV__avs_cra_writedata[54]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[1][22]~feeder ));
defparam \local_size_NO_SHIFT_REG[1][22]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[1][22]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[1][22]~feeder_I .lut_mask = "3333333333333333";

dffeas \local_size_NO_SHIFT_REG[1][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[1][22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[1][16]~10 ),
	.q(\local_size_NO_SHIFT_REG[1][22] ));
defparam \local_size_NO_SHIFT_REG[1][22]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[1][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[1][24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~78 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~78 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[1][30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[1][31] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73_I .lut_mask = "0000000000005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[31]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[30]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[27]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[29]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~DUPLICATE_I .created_from = "Q(max_local_id_1[28])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[30] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[27] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[29] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~4_I .lut_mask = "8000800000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[20]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[23]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[24]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[22]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[23] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[24] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[22] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[25] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~5_I .lut_mask = "CC00000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[21] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~4 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[20] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~5 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[26] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~6_I .lut_mask = "0000202000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[14]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[8]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[15]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[16]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[19]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[18]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[15] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[16] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[19] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[18] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[17] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~3_I .lut_mask = "C000000000000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~2 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~6 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[14] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[8] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~3 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~7_I .lut_mask = "0000000010100000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[4]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[6]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[5]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[4] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[7] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[6] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[5] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[3] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~1_I .lut_mask = "8800000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[0] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[2] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~7 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~1 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[1] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~8_I .lut_mask = "0000080800000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24]~8 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9_I .lut_mask = "1F1F1F1F0F0F0F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~DUPLICATE_I .created_from = "Q(local_id_1[6])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[8] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[7] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[7] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[8] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[6] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~3_I .lut_mask = "8008200240041001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[9] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[10] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[9] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[11] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[10] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[11] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~2_I .lut_mask = "8400210000840021";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[14] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[14] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[12] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[13] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[12] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[13] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~1_I .lut_mask = "9000090000900009";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~DUPLICATE_I .created_from = "Q(local_id_1[3])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[4] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[4] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[5] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[5] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[3] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~5_I .lut_mask = "8200008241000041";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~DUPLICATE_I .created_from = "Q(local_id_1[1])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[2] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1]~DUPLICATE ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[0] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[1] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[0] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[2] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~4_I .lut_mask = "8020080240100401";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~DUPLICATE_I .created_from = "Q(local_id_1[16])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~DUPLICATE_I .created_from = "Q(local_id_1[15])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[15] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16]~DUPLICATE ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[17] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[16] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[17] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~0_I .lut_mask = "8400210000840021";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~3 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~2 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~1 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~5 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~4 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~12 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~6 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~13_I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0_I (
	.dataa(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~13 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0_I .lut_mask = "55555555FFFFFFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~DUPLICATE_I .created_from = "Q(local_id_1[25])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[24] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[25] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[26] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[24] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[25] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[26] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~9_I .lut_mask = "8040201008040201";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[21] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[23] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[23] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[22] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[21] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[22] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~11_I .lut_mask = "8200410000820041";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[29]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add1~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_1[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[29] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[28] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[27] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[29] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[27] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[28] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~8_I .lut_mask = "8040080420100201";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[20] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[19] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[20] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[19] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[18] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[18] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~10_I .lut_mask = "8421000000008421";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~DUPLICATE_I .created_from = "Q(local_id_1[31])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~74 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~74 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add4~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[24]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_1[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_1[30] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[31] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_1[30] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~7_I .lut_mask = "8484848421212121";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~9 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~11 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~8 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~10 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~7 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal1~12_I .lut_mask = "0000000000000101";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][6]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[6]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][6]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][6]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][6]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][6]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][0]~0_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][0]~0 ));
defparam \local_size_NO_SHIFT_REG[2][0]~0_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][0]~0_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][0]~0_I .lut_mask = "0000001000000000";

dffeas \local_size_NO_SHIFT_REG[2][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][6]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][6] ));
defparam \local_size_NO_SHIFT_REG[2][6]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[5]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][5]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][5]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][5]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][5] ));
defparam \local_size_NO_SHIFT_REG[2][5]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[4]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][4]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][4]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][4]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][4] ));
defparam \local_size_NO_SHIFT_REG[2][4]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][4]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[3]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][3] ));
defparam \local_size_NO_SHIFT_REG[2][3]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][3]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[2]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][2] ));
defparam \local_size_NO_SHIFT_REG[2][2]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][2]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[1]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][1] ));
defparam \local_size_NO_SHIFT_REG[2][1]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][0]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[0]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][0]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][0]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][0]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][0] ));
defparam \local_size_NO_SHIFT_REG[2][0]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][0] ),
	.cin(gnd),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[2][1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[2][4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[25]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][25]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][25]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][25]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][25]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][24]~5_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[1]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][24]~5 ));
defparam \local_size_NO_SHIFT_REG[2][24]~5_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][24]~5_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][24]~5_I .lut_mask = "0000000000040000";

dffeas \local_size_NO_SHIFT_REG[2][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][25] ));
defparam \local_size_NO_SHIFT_REG[2][25]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][25]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[24]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][24] ));
defparam \local_size_NO_SHIFT_REG[2][24]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][23]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[23]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][23]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][23]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][23]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][23]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][16]~4_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][16]~4 ));
defparam \local_size_NO_SHIFT_REG[2][16]~4_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][16]~4_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][16]~4_I .lut_mask = "0000000001000000";

dffeas \local_size_NO_SHIFT_REG[2][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][23]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][23] ));
defparam \local_size_NO_SHIFT_REG[2][23]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][22]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[22]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][22]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][22]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][22]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][22] ));
defparam \local_size_NO_SHIFT_REG[2][22]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][22]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[21]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][21] ));
defparam \local_size_NO_SHIFT_REG[2][21]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[20]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][20]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][20]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][20]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][20] ));
defparam \local_size_NO_SHIFT_REG[2][20]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][19]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[19]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][19]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][19]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][19]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][19]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][19] ));
defparam \local_size_NO_SHIFT_REG[2][19]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[18]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][18]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][18]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][18]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][18] ));
defparam \local_size_NO_SHIFT_REG[2][18]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][18]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][17] ));
defparam \local_size_NO_SHIFT_REG[2][17]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][17]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[16]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][16]~4 ),
	.q(\local_size_NO_SHIFT_REG[2][16] ));
defparam \local_size_NO_SHIFT_REG[2][16]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][8]~3_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][8]~3 ));
defparam \local_size_NO_SHIFT_REG[2][8]~3_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][8]~3_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][8]~3_I .lut_mask = "0001000000000000";

dffeas \local_size_NO_SHIFT_REG[2][15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[15]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][15] ));
defparam \local_size_NO_SHIFT_REG[2][15]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][15]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[14]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][14] ));
defparam \local_size_NO_SHIFT_REG[2][14]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][14]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][13] ));
defparam \local_size_NO_SHIFT_REG[2][13]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][12]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[12]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][12]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][12]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][12]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][12] ));
defparam \local_size_NO_SHIFT_REG[2][12]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[11]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][11]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][11]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][11]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][11] ));
defparam \local_size_NO_SHIFT_REG[2][11]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][11]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][10] ));
defparam \local_size_NO_SHIFT_REG[2][10]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][10]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[9]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][9] ));
defparam \local_size_NO_SHIFT_REG[2][9]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[8]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][8]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][8]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][8]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][8]~3 ),
	.q(\local_size_NO_SHIFT_REG[2][8] ));
defparam \local_size_NO_SHIFT_REG[2][8]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][8]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[7]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][0]~0 ),
	.q(\local_size_NO_SHIFT_REG[2][7] ));
defparam \local_size_NO_SHIFT_REG[2][7]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[2][8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[2][9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[2][11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[2][21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[2][23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[4]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[5]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[7] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[4] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[5] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[3] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[6] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~1_I .lut_mask = "8080000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[19]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[15]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[16]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[17]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[19] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[15] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[16] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[17] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[18] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~3_I .lut_mask = "8080000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[12]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[11]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[13]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[10]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[12] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[11] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[13] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[10] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[9] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~2_I .lut_mask = "8080000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[14]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[20]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[26]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][26] ));
defparam \local_size_NO_SHIFT_REG[2][26]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[26]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[22]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[25] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[22] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[24] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~5_I .lut_mask = "CC00000000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[21]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[31]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][31] ));
defparam \local_size_NO_SHIFT_REG[2][31]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][31]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[30]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][30] ));
defparam \local_size_NO_SHIFT_REG[2][30]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \local_size_NO_SHIFT_REG[2][29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[29]~input0 ),
	.combout(\local_size_NO_SHIFT_REG[2][29]~feeder ));
defparam \local_size_NO_SHIFT_REG[2][29]~feeder_I .shared_arith = "off";
defparam \local_size_NO_SHIFT_REG[2][29]~feeder_I .extended_lut = "off";
defparam \local_size_NO_SHIFT_REG[2][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \local_size_NO_SHIFT_REG[2][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\local_size_NO_SHIFT_REG[2][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][29] ));
defparam \local_size_NO_SHIFT_REG[2][29]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][29]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[28]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][28] ));
defparam \local_size_NO_SHIFT_REG[2][28]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][28]~I .is_wysiwyg = "true";

dffeas \local_size_NO_SHIFT_REG[2][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[27]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\local_size_NO_SHIFT_REG[2][24]~5 ),
	.q(\local_size_NO_SHIFT_REG[2][27] ));
defparam \local_size_NO_SHIFT_REG[2][27]~I .power_up = "low";
defparam \local_size_NO_SHIFT_REG[2][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~78 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[2][28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~78 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[2][30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[2][31] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73_I .lut_mask = "0000000000000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[31]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[30]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[27]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[30] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[27] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[28] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~4_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[20] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[26] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~5 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[21] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~4 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~6_I .lut_mask = "0000000008080000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~3 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~2 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[14] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~6 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[8] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~7_I .lut_mask = "0000101000000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[1]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0_I (
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[2][0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~1 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~7 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[1] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[2] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~8_I .lut_mask = "1000100000000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datad(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0]~8 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9_I .lut_mask = "01FF01FF00FF00FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~118 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~118 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~122 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~122 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~126 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~126 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[25] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[25] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[26] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[24] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[26] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[24] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~9_I .lut_mask = "9000090000900009";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[29]~DUPLICATE_I .created_from = "Q(max_local_id_2[29])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~DUPLICATE_I .created_from = "Q(local_id_2[27])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~86 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[28]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[29] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~86 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[29]~DUPLICATE ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[28] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[28] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[27] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[27] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[29] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~8_I .lut_mask = "8200008241000041";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add2~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_2[23]~DUPLICATE_I .created_from = "Q(max_local_id_2[23])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[21] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[23] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[22] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[22] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[21] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[23]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~11_I .lut_mask = "8008400420021001";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~DUPLICATE_I .created_from = "Q(local_id_2[31])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[30] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~74 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~74 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77_I .lut_mask = "0000FFFF00005555";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[31] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[30] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[31] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[30] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~7_I .lut_mask = "8844884422112211";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[20] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[20] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[19] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[18] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[19] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[18] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~10_I .lut_mask = "9000090000900009";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~9 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~8 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~11 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~7 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~10 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~12_I .lut_mask = "0000000000000101";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~6 ),
	.datad(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~12 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0_I .lut_mask = "00FF00FF0FFF0FFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~DUPLICATE_I .created_from = "Q(local_id_2[3])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65_I .lut_mask = "0000FFFF00003333";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[8]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[6]~DUPLICATE_I .created_from = "Q(local_id_2[6])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[6] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[8] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[7] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[7] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[6]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[8] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~3_I .lut_mask = "8008400420021001";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[4] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[5] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[5] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[3] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[3] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[4] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~5_I .lut_mask = "8200008241000041";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[2] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[2] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[1] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[0] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[1] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~4_I .lut_mask = "9000090000900009";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[10] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[9] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[10] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[11] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[11] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[9] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~2_I .lut_mask = "8400008421000021";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add5~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[0]~9 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|local_id_2[17]~DUPLICATE_I .created_from = "Q(local_id_2[17])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[17] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[15] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[15] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[16] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[16] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[17]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~0_I .lut_mask = "8200008241000041";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[12] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[13] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[14] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[13] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__local_id_2[12] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_2[14] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~1_I .lut_mask = "8020401008020401";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~3 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~5 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~4 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~2 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~1 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Equal2~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~12 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~6 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~6 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~12 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal2~12 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal1~6 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|valid_rreq~0_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4_I .lut_mask = "CCCCCCCCC3C3C3C3";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1~I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1~I .lut_mask = "0000F0F0000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~4 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_rg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~1_I .lut_mask = "0505050505050505";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~1 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3_I .lut_mask = "22FF22FF20F020F0";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~57_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][0] ),
	.cin(gnd),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~57_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~9 ),
	.dataf(__ALT_INV__start_NO_SHIFT_REG),
	.combout(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0_I .lut_mask = "00FF00FFFFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[62]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][30]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][30]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][30]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][24]~5_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[7]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][24]~5 ));
defparam \num_groups_NO_SHIFT_REG[0][24]~5_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][24]~5_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][24]~5_I .lut_mask = "0000000000000002";

dffeas \num_groups_NO_SHIFT_REG[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][30] ));
defparam \num_groups_NO_SHIFT_REG[0][30]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[61]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][29]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][29]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][29]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][29] ));
defparam \num_groups_NO_SHIFT_REG[0][29]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][28]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[60]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][28]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][28]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][28]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][28]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][28] ));
defparam \num_groups_NO_SHIFT_REG[0][28]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][28]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[59]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][27] ));
defparam \num_groups_NO_SHIFT_REG[0][27]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][27]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[58]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][26] ));
defparam \num_groups_NO_SHIFT_REG[0][26]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[57]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][25]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][25]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][25]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][25] ));
defparam \num_groups_NO_SHIFT_REG[0][25]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][24]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[56]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][24]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][24]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][24]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][24]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][24] ));
defparam \num_groups_NO_SHIFT_REG[0][24]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][16]~3_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_write~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[6]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][16]~3 ));
defparam \num_groups_NO_SHIFT_REG[0][16]~3_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][16]~3_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][16]~3_I .lut_mask = "0000000000000002";

dffeas \num_groups_NO_SHIFT_REG[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[55]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][23] ));
defparam \num_groups_NO_SHIFT_REG[0][23]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][22]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[54]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][22]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][22]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][22]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][22] ));
defparam \num_groups_NO_SHIFT_REG[0][22]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][22]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[53]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][21] ));
defparam \num_groups_NO_SHIFT_REG[0][21]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[52]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][20]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][20]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][20]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][20] ));
defparam \num_groups_NO_SHIFT_REG[0][20]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][20]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[51]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][19] ));
defparam \num_groups_NO_SHIFT_REG[0][19]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[50]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][18]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][18]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][18]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][18] ));
defparam \num_groups_NO_SHIFT_REG[0][18]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][17]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[49]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][17]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][17]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][17]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][17]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][17] ));
defparam \num_groups_NO_SHIFT_REG[0][17]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][17]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[48]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][16]~3 ),
	.q(\num_groups_NO_SHIFT_REG[0][16] ));
defparam \num_groups_NO_SHIFT_REG[0][16]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][15]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[47]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][15]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][15]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][15]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][8]~4_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[5]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][8]~4 ));
defparam \num_groups_NO_SHIFT_REG[0][8]~4_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][8]~4_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][8]~4_I .lut_mask = "0000000000000100";

dffeas \num_groups_NO_SHIFT_REG[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][15]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][15] ));
defparam \num_groups_NO_SHIFT_REG[0][15]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][15]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[46]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][14] ));
defparam \num_groups_NO_SHIFT_REG[0][14]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][13]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[45]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][13]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][13]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][13]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][13]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][13] ));
defparam \num_groups_NO_SHIFT_REG[0][13]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][12]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[44]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][12]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][12]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][12]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][12] ));
defparam \num_groups_NO_SHIFT_REG[0][12]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[43]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][11]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][11]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][11]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][11] ));
defparam \num_groups_NO_SHIFT_REG[0][11]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][10]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[42]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][10]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][10]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][10]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][10]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][10] ));
defparam \num_groups_NO_SHIFT_REG[0][10]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][10]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[41]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][9] ));
defparam \num_groups_NO_SHIFT_REG[0][9]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[40]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][8]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][8]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][8]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][8]~4 ),
	.q(\num_groups_NO_SHIFT_REG[0][8] ));
defparam \num_groups_NO_SHIFT_REG[0][8]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][0]~0_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[4]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][0]~0 ));
defparam \num_groups_NO_SHIFT_REG[0][0]~0_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][0]~0_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][0]~0_I .lut_mask = "0000000000000010";

dffeas \num_groups_NO_SHIFT_REG[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[39]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][7] ));
defparam \num_groups_NO_SHIFT_REG[0][7]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][7]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[38]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][6] ));
defparam \num_groups_NO_SHIFT_REG[0][6]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][6]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[37]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][5] ));
defparam \num_groups_NO_SHIFT_REG[0][5]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[36]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][4]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][4]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][4]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][4] ));
defparam \num_groups_NO_SHIFT_REG[0][4]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[0][3]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[35]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[0][3]~feeder ));
defparam \num_groups_NO_SHIFT_REG[0][3]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[0][3]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[0][3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][3] ));
defparam \num_groups_NO_SHIFT_REG[0][3]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][3]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[34]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][2] ));
defparam \num_groups_NO_SHIFT_REG[0][2]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][2]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[33]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][1] ));
defparam \num_groups_NO_SHIFT_REG[0][1]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][1]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[32]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][0]~0 ),
	.q(\num_groups_NO_SHIFT_REG[0][0] ));
defparam \num_groups_NO_SHIFT_REG[0][0]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~126_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][0] ),
	.cin(gnd),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~126_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~126_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~126_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~57_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~57_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~49_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~49_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~61_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[0][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~61_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~65_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][4] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~65_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~53_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~53_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~41_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][6] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~41_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~45_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~45_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~37_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~37_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~29_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~29_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~33_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~33_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~25_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~25_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~17_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~17_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~21_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~21_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~13_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~13_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~5_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~5_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~9_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~9_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~1_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~1_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~109_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~109_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~113_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~113_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~101_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~101_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~117_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~117_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~121_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~121_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~105_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~93_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[0][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~93_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~97_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~97_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~89_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~89_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~81_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~81 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~82 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~81_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~85_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[0][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~82 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~85_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~69_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~69_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~73_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add0~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~73_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][30]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[63]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[0][24]~5 ),
	.q(\num_groups_NO_SHIFT_REG[0][31] ));
defparam \num_groups_NO_SHIFT_REG[0][31]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[0][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add0~77_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[0][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add0~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add0~77 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add0~77_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~57_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][0] ),
	.cin(gnd),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~57_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0_I (
	.datac(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~9 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0_I .lut_mask = "0F0F0F0FFFFFFFFF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~DUPLICATE ),
	.datae(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1_I .lut_mask = "0000FFFFC0C0FFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~61_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~61_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~49_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~49_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~65_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~69_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~69_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~DUPLICATE_I .created_from = "Q(group_id[0][4])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~53_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~41_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~41_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~DUPLICATE_I .created_from = "Q(group_id[0][6])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~45_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~37_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~29_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~33_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~25_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~25_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~17_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~21_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~21_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~13_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~13_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~5_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~9_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~9_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~1_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~113_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~117_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~117_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~105_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~121_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~121_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~125_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~125 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~125_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~125_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~125_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~109_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~97_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~97_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~101_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~101_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~93_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~85_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~85_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~89_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~73_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~73_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~77_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~77 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add3~78 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~77_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][30]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add3~81_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add3~78 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add3~81 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add3~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][31]~DUPLICATE_I .created_from = "Q(group_id[0][31])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~5_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][30] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][31] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][30] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][31]~DUPLICATE ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~5 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~5_I .lut_mask = "C0C030300C0C0303";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][29]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][11]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][29]~DUPLICATE_I .created_from = "Q(group_id[0][29])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~12_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][11] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][14] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][29] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][11] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][29]~DUPLICATE ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][14] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~12 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~12_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~12_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~12_I .lut_mask = "8040080420100201";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][15]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~0_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][15] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][15] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][16] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][16] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~0_I .lut_mask = "A500A50000A500A5";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][12]~DUPLICATE_I .created_from = "Q(group_id[0][12])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][13]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~1_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][12]~DUPLICATE ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][13] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][13] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][12] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~1_I .lut_mask = "C0C00C0C30300303";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][10]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~2_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][10] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][10] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][9] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][9] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~2_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~2_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~2_I .lut_mask = "A5A500000000A5A5";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][17]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][27]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~6_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][28] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][27] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][27] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][28] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~6_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~6_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~6_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~13_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][17] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~1 ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~2 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][17] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~6 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~13 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~13_I .lut_mask = "0000000002020101";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][20]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][24]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~15_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][20] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][23] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][20] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][24] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][24] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][23] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~15 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~15_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~15_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~15_I .lut_mask = "8400008421000021";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][25]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][19]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~14_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][19] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][25] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][25] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][18] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][19] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][18] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~14_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~14_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~14_I .lut_mask = "8200410000820041";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][26]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][21]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~7_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][22] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][21] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][21] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][22] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~7 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~7_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~7_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~7_I .lut_mask = "C00CC00C30033003";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~8_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][26] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~15 ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~14 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][26] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~7 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~8 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~8_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~8_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~8_I .lut_mask = "0000000002020101";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][4]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][4]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~3_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][4] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][3] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][4] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][3] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~3 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~3_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~3_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~3_I .lut_mask = "C030C0300C030C03";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0_I (
	.dataf(\__ALT_INV__num_groups_NO_SHIFT_REG[0][0] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][0]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][1]~DUPLICATE_I .created_from = "Q(group_id[0][1])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][1]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~10_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][0] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][0] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][1]~DUPLICATE ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][1] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][7] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][7] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~10_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~10_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~10_I .lut_mask = "9009000000009009";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][2]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add3~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[0][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[0][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add0~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[0][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~11_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][2] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][2] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][5] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][6] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][6] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][5] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~11 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~11_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~11_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~11_I .lut_mask = "9000009009000009";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~4_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~3 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[0][8] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[0][8] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~10 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~11 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~4 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~4_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~4_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~4_I .lut_mask = "0000000000410041";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal0~9_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~5 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~12 ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~0 ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~13 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~8 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~4 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal0~9 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal0~9_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups ),
	.datae(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~9 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1_I .lut_mask = "0000FFFF2020FFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~61_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~61_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~49_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~49_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~65_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~69_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][4] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~69_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~53_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~41_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][6] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~41_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~45_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~37_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~29_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~33_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~25_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~25_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~17_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~21_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~21_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~13_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~13_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~5_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][8]~7_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][8]~7 ));
defparam \num_groups_NO_SHIFT_REG[1][8]~7_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][8]~7_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][8]~7_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[1][15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[15]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][15] ));
defparam \num_groups_NO_SHIFT_REG[1][15]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][15]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[14]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][14] ));
defparam \num_groups_NO_SHIFT_REG[1][14]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][14]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][13] ));
defparam \num_groups_NO_SHIFT_REG[1][13]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][12]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[12]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][12]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][12]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][12]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][12] ));
defparam \num_groups_NO_SHIFT_REG[1][12]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[11]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][11]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][11]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][11]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][11] ));
defparam \num_groups_NO_SHIFT_REG[1][11]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][11]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][10] ));
defparam \num_groups_NO_SHIFT_REG[1][10]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][10]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[9]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][9] ));
defparam \num_groups_NO_SHIFT_REG[1][9]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[8]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][8]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][8]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][8]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][8]~7 ),
	.q(\num_groups_NO_SHIFT_REG[1][8] ));
defparam \num_groups_NO_SHIFT_REG[1][8]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][0]~1_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][0]~1 ));
defparam \num_groups_NO_SHIFT_REG[1][0]~1_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][0]~1_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][0]~1_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[1][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[7]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][7] ));
defparam \num_groups_NO_SHIFT_REG[1][7]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][6]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[6]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][6]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][6]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][6]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][6]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][6] ));
defparam \num_groups_NO_SHIFT_REG[1][6]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[5]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][5]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][5]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][5]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][5] ));
defparam \num_groups_NO_SHIFT_REG[1][5]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[4]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][4]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][4]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][4]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][4] ));
defparam \num_groups_NO_SHIFT_REG[1][4]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][4]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[3]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][3] ));
defparam \num_groups_NO_SHIFT_REG[1][3]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][3]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[2]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][2] ));
defparam \num_groups_NO_SHIFT_REG[1][2]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][2]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[1]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][1] ));
defparam \num_groups_NO_SHIFT_REG[1][1]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][1]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[0]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][0]~1 ),
	.q(\num_groups_NO_SHIFT_REG[1][0] ));
defparam \num_groups_NO_SHIFT_REG[1][0]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~126_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][0] ),
	.cin(gnd),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~126_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~126_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~126_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~57_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~57_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~49_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~49_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~61_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[1][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~61_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~65_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][4] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~65_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~53_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~53_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~41_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][6] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~41_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~45_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~45_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~37_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~37_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~29_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[1][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~29_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~33_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~33_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~25_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~25_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~17_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~17_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~21_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[1][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~21_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~13_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~13_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~5_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~5_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][16]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[16]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][16]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][16]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][16]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][16]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][16]~6_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][16]~6 ));
defparam \num_groups_NO_SHIFT_REG[1][16]~6_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][16]~6_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][16]~6_I .lut_mask = "0010000000000000";

dffeas \num_groups_NO_SHIFT_REG[1][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][16]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][16] ));
defparam \num_groups_NO_SHIFT_REG[1][16]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~9_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~9_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~9_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~9_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~0_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][15] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][15] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][16] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][16] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~0_I .lut_mask = "C3C300000000C3C3";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~1_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~113_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~117_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~117_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~105_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~121_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~121_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~125_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~125 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~125_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~125_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~125_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~109_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~97_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~97_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~101_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~101_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~93_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~85_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~85_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~89_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~73_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~73_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~77_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~77 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add4~78 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~77_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add4~81_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add4~78 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add4~81 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add4~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][31]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[31]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][31]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][31]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][31]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][31]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][24]~8_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][24]~8 ));
defparam \num_groups_NO_SHIFT_REG[1][24]~8_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][24]~8_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][24]~8_I .lut_mask = "0000000800000000";

dffeas \num_groups_NO_SHIFT_REG[1][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][31]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][31] ));
defparam \num_groups_NO_SHIFT_REG[1][31]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[30]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][30]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][30]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][30]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][30] ));
defparam \num_groups_NO_SHIFT_REG[1][30]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[29]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][29]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][29]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][29]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][29] ));
defparam \num_groups_NO_SHIFT_REG[1][29]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][29]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[28]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][28] ));
defparam \num_groups_NO_SHIFT_REG[1][28]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][28]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[27]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][27] ));
defparam \num_groups_NO_SHIFT_REG[1][27]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][27]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[26]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][26] ));
defparam \num_groups_NO_SHIFT_REG[1][26]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[25]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][25]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][25]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][25]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][25] ));
defparam \num_groups_NO_SHIFT_REG[1][25]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][25]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[24]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][24]~8 ),
	.q(\num_groups_NO_SHIFT_REG[1][24] ));
defparam \num_groups_NO_SHIFT_REG[1][24]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][23]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[23]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][23]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][23]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][23]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][23]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][23] ));
defparam \num_groups_NO_SHIFT_REG[1][23]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][23]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[22]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][22] ));
defparam \num_groups_NO_SHIFT_REG[1][22]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][22]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[21]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][21] ));
defparam \num_groups_NO_SHIFT_REG[1][21]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[20]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][20]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][20]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][20]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][20] ));
defparam \num_groups_NO_SHIFT_REG[1][20]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][19]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[19]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][19]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][19]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][19]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][19]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][19] ));
defparam \num_groups_NO_SHIFT_REG[1][19]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[1][18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[18]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[1][18]~feeder ));
defparam \num_groups_NO_SHIFT_REG[1][18]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[1][18]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[1][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[1][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[1][18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][18] ));
defparam \num_groups_NO_SHIFT_REG[1][18]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][18]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[1][17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[1][16]~6 ),
	.q(\num_groups_NO_SHIFT_REG[1][17] ));
defparam \num_groups_NO_SHIFT_REG[1][17]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[1][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~1_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~1_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~109_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[1][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~109_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~113_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~113_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~101_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[1][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~101_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~117_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~117_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~121_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[1][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~121_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~105_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~93_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~93_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~97_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~97_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~89_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~89_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~81_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[1][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~81 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~82 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~81_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~85_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[1][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~82 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~85_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~69_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[1][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~69_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~73_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add1~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~73_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add1~77_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[1][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add1~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add1~77 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add1~77_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][31]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~5_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][31] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][31] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][30] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][30] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~5 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~5_I .lut_mask = "A5A500000000A5A5";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][2]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~11_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][6] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][2] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][5] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][6] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][5] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][2] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~11 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~11_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~11_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~11_I .lut_mask = "8040080420100201";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][8]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][1]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][1]~DUPLICATE_I .created_from = "Q(group_id[1][1])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1_I (
	.dataf(\__ALT_INV__num_groups_NO_SHIFT_REG[1][0] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][0]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~10_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][1] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][1]~DUPLICATE ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][0] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][7] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][0] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][7] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~10_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~10_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~10_I .lut_mask = "9000090000900009";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][3]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~3_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][3] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][4] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][3] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][4] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~3 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~3_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~3_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~3_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~4_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~11 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][8] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][8] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~10 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~3 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~4 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~4_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~4_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~4_I .lut_mask = "0000000000410041";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][23]~DUPLICATE_I .created_from = "Q(group_id[1][23])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][24]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][20]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~15_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][23]~DUPLICATE ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][20] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][24] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][24] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][20] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][23] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~15 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~15_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~15_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~15_I .lut_mask = "8008200240041001";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][26]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][19]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][18]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~14_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][19] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][18] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][25] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][25] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][19] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][18] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~14_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~14_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~14_I .lut_mask = "8008400420021001";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][21]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~7_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][21] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][22] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][21] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][22] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~7 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~7_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~7_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~7_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~8_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~15 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][26] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][26] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~14 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~7 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~8 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~8_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~8_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~8_I .lut_mask = "0000000000410041";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][29]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][11]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~12_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][29] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][11] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][14] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][14] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][29] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][11] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~12 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~12_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~12_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~12_I .lut_mask = "8008400420021001";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][13]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][12]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add4~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[1][24]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[1][12]~DUPLICATE_I .created_from = "Q(group_id[1][12])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~1_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][13] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][12] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][12]~DUPLICATE ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][13] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~1_I .lut_mask = "C00CC00C30033003";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][17]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][27]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~6_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][27] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][27] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][28] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][28] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~6_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~6_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~6_I .lut_mask = "A500A50000A500A5";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][9]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add1~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[1][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~2_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][9] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][10] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][10] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][9] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~2_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~2_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~2_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~13_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~1 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[1][17] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~6 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~2 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[1][17] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~13 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~13_I .lut_mask = "0000004400000011";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal1~9_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~0 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~5 ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~4 ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~8 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~12 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~13 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal1~9 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal1~9_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal1~9 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal0~9 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~0_I .lut_mask = "00000000000000C0";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2_I (
	.datae(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~9 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2_I .lut_mask = "0000FFFFFFFFFFFF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3_I (
	.datab(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~0 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3_I .lut_mask = "33333333FFFFFFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~57_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][0] ),
	.cin(gnd),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~57_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~61_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~61_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~49_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~49_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~65_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~69_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~69_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~DUPLICATE_I .created_from = "Q(group_id[2][4])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~53_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~DUPLICATE_I .created_from = "Q(group_id[2][5])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~41_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~41_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~DUPLICATE_I .created_from = "Q(group_id[2][6])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~45_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~37_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~DUPLICATE_I .created_from = "Q(group_id[2][8])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~29_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~29_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~33_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~25_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~25_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~17_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~21_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~21_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~13_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~13_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~5_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~9_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~9_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~1_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~1_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][17]~DUPLICATE_I .created_from = "Q(group_id[2][17])";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][17]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[49]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][17]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][17]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][17]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][17]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][16]~9_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[6]~input0 ),
	.dataf(\__ALT_INV__avs_cra_write~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][16]~9 ));
defparam \num_groups_NO_SHIFT_REG[2][16]~9_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][16]~9_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][16]~9_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[2][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][17]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][17] ));
defparam \num_groups_NO_SHIFT_REG[2][17]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][17]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[48]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][16] ));
defparam \num_groups_NO_SHIFT_REG[2][16]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][8]~10_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[5]~input0 ),
	.dataf(\__ALT_INV__avs_cra_write~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][8]~10 ));
defparam \num_groups_NO_SHIFT_REG[2][8]~10_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][8]~10_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][8]~10_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[2][15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[47]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][15] ));
defparam \num_groups_NO_SHIFT_REG[2][15]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][14]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[46]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][14]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][14]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][14]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][14]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][14] ));
defparam \num_groups_NO_SHIFT_REG[2][14]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][14]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[45]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][13] ));
defparam \num_groups_NO_SHIFT_REG[2][13]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][13]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[44]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][12] ));
defparam \num_groups_NO_SHIFT_REG[2][12]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[43]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][11]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][11]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][11]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][11] ));
defparam \num_groups_NO_SHIFT_REG[2][11]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][11]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[42]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][10] ));
defparam \num_groups_NO_SHIFT_REG[2][10]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][10]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[41]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][9] ));
defparam \num_groups_NO_SHIFT_REG[2][9]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[40]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][8]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][8]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][8]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][8]~10 ),
	.q(\num_groups_NO_SHIFT_REG[2][8] ));
defparam \num_groups_NO_SHIFT_REG[2][8]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][7]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[39]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][7]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][7]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][7]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][0]~2_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[4]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][0]~2 ));
defparam \num_groups_NO_SHIFT_REG[2][0]~2_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][0]~2_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][0]~2_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[2][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][7] ));
defparam \num_groups_NO_SHIFT_REG[2][7]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][7]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[38]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][6] ));
defparam \num_groups_NO_SHIFT_REG[2][6]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[37]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][5]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][5]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][5]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][5] ));
defparam \num_groups_NO_SHIFT_REG[2][5]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[36]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][4]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][4]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][4]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][4] ));
defparam \num_groups_NO_SHIFT_REG[2][4]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][3]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[35]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][3]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][3]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][3]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][3] ));
defparam \num_groups_NO_SHIFT_REG[2][3]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][2]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[34]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][2]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][2]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][2]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][2]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][2] ));
defparam \num_groups_NO_SHIFT_REG[2][2]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][1]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[33]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][1]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][1]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][1]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][1]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][1] ));
defparam \num_groups_NO_SHIFT_REG[2][1]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][1]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[32]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][0]~2 ),
	.q(\num_groups_NO_SHIFT_REG[2][0] ));
defparam \num_groups_NO_SHIFT_REG[2][0]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~126_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[2][0] ),
	.cin(gnd),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~126_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~126_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~126_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~57_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[2][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~57_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~49_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[2][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~49_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~61_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~61_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~65_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][4] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~65_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~53_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~53_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~41_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][6] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~41_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~45_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[2][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~45_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~37_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~37_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~29_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~29_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~33_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][10] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~33_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~25_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][11] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~25_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~17_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~17_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~21_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~21_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~13_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~13_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~5_I (
	.datad(\__ALT_INV__num_groups_NO_SHIFT_REG[2][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~5_I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~9_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~9_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~1_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~1_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][17]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][13]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][12]~DUPLICATE_I .created_from = "Q(group_id[2][12])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~1_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][13] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][13] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][12]~DUPLICATE ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][12] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~1_I .lut_mask = "A500A50000A500A5";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][10]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~2_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][9] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][10] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][10] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][9] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~2_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~2_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~2_I .lut_mask = "C0C00C0C30300303";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~DUPLICATE_I .created_from = "Q(group_id[2][28])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~113_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~117_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~117_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~117 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~105_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~121_I (
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~121_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~121 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~125_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~125 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~126 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~125_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~125_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~125_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~109_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~126 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~109_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~97_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~97_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~101_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~101_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~93_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~85_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~89_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][28]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[60]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][28]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][28]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][28]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][28]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][24]~11_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[7]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][24]~11 ));
defparam \num_groups_NO_SHIFT_REG[2][24]~11_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][24]~11_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][24]~11_I .lut_mask = "0000000000004000";

dffeas \num_groups_NO_SHIFT_REG[2][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][28]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][28] ));
defparam \num_groups_NO_SHIFT_REG[2][28]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][27]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[59]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][27]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][27]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][27]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][27]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][27]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][27] ));
defparam \num_groups_NO_SHIFT_REG[2][27]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][26]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[58]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][26]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][26]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][26]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][26]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][26] ));
defparam \num_groups_NO_SHIFT_REG[2][26]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][26]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[57]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][25] ));
defparam \num_groups_NO_SHIFT_REG[2][25]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][25]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[56]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][24] ));
defparam \num_groups_NO_SHIFT_REG[2][24]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][24]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[55]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][23] ));
defparam \num_groups_NO_SHIFT_REG[2][23]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][23]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[54]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][22] ));
defparam \num_groups_NO_SHIFT_REG[2][22]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][22]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[53]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][21] ));
defparam \num_groups_NO_SHIFT_REG[2][21]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][21]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[52]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][20] ));
defparam \num_groups_NO_SHIFT_REG[2][20]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][19]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[51]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][19]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][19]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][19]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][19]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][19] ));
defparam \num_groups_NO_SHIFT_REG[2][19]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[50]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][18]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][18]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][18]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][16]~9 ),
	.q(\num_groups_NO_SHIFT_REG[2][18] ));
defparam \num_groups_NO_SHIFT_REG[2][18]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~109_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~109_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~113_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[2][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~113_I .lut_mask = "0000000000005555";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~101_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[2][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~101_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~117_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~117 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~118 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~117_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~117_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~117_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~121_I (
	.datab(\__ALT_INV__num_groups_NO_SHIFT_REG[2][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~118 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~121 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~122 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~121_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~121_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~121_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~105_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][23] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~122 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~105_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~93_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~93_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~97_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][25] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~97_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~89_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~89_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~81_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~81 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~82 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~81_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~85_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~82 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~85 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~86 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~85_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~85 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][28]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~81 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~6_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][28] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][27] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][28] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][27] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~6_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~6_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~6_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~13_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][17]~DUPLICATE ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][17] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~1 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~2 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~6 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~13 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~13_I .lut_mask = "0000000000000909";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][8]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~41 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~49 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][2]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][5]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~53 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~11_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][6] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][6] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][2] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][2] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][5] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][5] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~11 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~11_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~11_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~11_I .lut_mask = "9009000000009009";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][8]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][4]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~61 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][3]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~65 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~3_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][3] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][4] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][3] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][4] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~3 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~3_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~3_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~3_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2_I (
	.dataf(\__ALT_INV__num_groups_NO_SHIFT_REG[2][0] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][0]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~57 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][1]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~45 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~10_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][1] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][0] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][7] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][0] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][1] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][7] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~10_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~10_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~10_I .lut_mask = "8020401008020401";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~4_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][8] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~11 ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][8] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~3 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~10 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~4 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~4_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~4_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~4_I .lut_mask = "0000000000000A05";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][15]~DUPLICATE_I .created_from = "Q(group_id[2][15])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][15]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~0_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][16] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][15]~DUPLICATE ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][15] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][16] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~0_I .lut_mask = "C0C00C0C30300303";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[61]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][29]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][29]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][29]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][29] ));
defparam \num_groups_NO_SHIFT_REG[2][29]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~69_I (
	.dataa(\__ALT_INV__num_groups_NO_SHIFT_REG[2][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~86 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~69_I .lut_mask = "0000000000005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~69 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~73_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][29] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~73_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][29] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][29]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][29]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][11]~DUPLICATE_I .created_from = "Q(group_id[2][11])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~12_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][14] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][14] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][29] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][29] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][11]~DUPLICATE ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][11] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~12 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~12_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~12_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~12_I .lut_mask = "9009000000009009";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~77_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~77 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add5~78 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~77_I .lut_mask = "0000FFFF00003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add5~81_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add5~78 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add5~81 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add5~81_I .lut_mask = "0000FFFF00005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][31]~I .is_wysiwyg = "true";

dffeas \num_groups_NO_SHIFT_REG[2][31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[63]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][31] ));
defparam \num_groups_NO_SHIFT_REG[2][31]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \num_groups_NO_SHIFT_REG[2][30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[62]~input0 ),
	.combout(\num_groups_NO_SHIFT_REG[2][30]~feeder ));
defparam \num_groups_NO_SHIFT_REG[2][30]~feeder_I .shared_arith = "off";
defparam \num_groups_NO_SHIFT_REG[2][30]~feeder_I .extended_lut = "off";
defparam \num_groups_NO_SHIFT_REG[2][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \num_groups_NO_SHIFT_REG[2][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\num_groups_NO_SHIFT_REG[2][30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\num_groups_NO_SHIFT_REG[2][24]~11 ),
	.q(\num_groups_NO_SHIFT_REG[2][30] ));
defparam \num_groups_NO_SHIFT_REG[2][30]~I .power_up = "low";
defparam \num_groups_NO_SHIFT_REG[2][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~73_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][30] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add2~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~73_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add2~77_I (
	.datac(\__ALT_INV__num_groups_NO_SHIFT_REG[2][31] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add2~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add2~77 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add2~77_I .lut_mask = "0000000000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~77 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][31]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~73 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~5_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][31] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][30] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][31] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][30] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~5 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~5_I .lut_mask = "A050A0500A050A05";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~105 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][23]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][24]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~101 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~15_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][24] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][23] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][23] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][24] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][20] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][20] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~15 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~15_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~15_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~15_I .lut_mask = "8241000000008241";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][26]~DUPLICATE_I .created_from = "Q(group_id[2][26])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~89 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][26]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~109 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][18]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~113 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][19]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][25]~DUPLICATE_I .created_from = "Q(group_id[2][25])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~97 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~14_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][18] ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][18] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][19] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][25]~DUPLICATE ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][19] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][25] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~14_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~14_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~14_I .lut_mask = "9000090000900009";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~121 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][22]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add5~125 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~2 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|group_id[2][3]~3 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|group_id[2][22]~DUPLICATE_I .created_from = "Q(group_id[2][22])";

dffeas \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add2~117 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|max_group_id[2][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~7_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][22] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][22]~DUPLICATE ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][21] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][21] ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~7 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~7_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~7_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~7_I .lut_mask = "C3C300000000C3C3";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~8_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~15 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__group_id[2][26]~DUPLICATE ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__max_group_id[2][26] ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~14 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~7 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~8 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~8_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~8_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~8_I .lut_mask = "0000000000004141";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Equal2~9_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~13 ),
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~4 ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~0 ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~12 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~5 ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~8 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|Equal2~9 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Equal2~9_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~0 ),
	.datae(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__Equal2~9 ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1 ));
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1_I .lut_mask = "0000FFFF0F0FFFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups~DUPLICATE_I .created_from = "Q(dispatched_all_groups)";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|started~0_I (
	.datae(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~DUPLICATE ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|started~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|started~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|started~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|started~0_I .lut_mask = "0000FFFFFFFFFFFF";

dffeas \acl_work_group_dispatcher:group_dispatcher|started~I (
	.clk(\clock~CLKENA0 ),
	.asdata(start_NO_SHIFT_REG),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\acl_work_group_dispatcher:group_dispatcher|started~0 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|started ));
defparam \acl_work_group_dispatcher:group_dispatcher|started~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|started~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|delayed_start~0_I (
	.dataa(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__started ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|delayed_start~0 ));
defparam \acl_work_group_dispatcher:group_dispatcher|delayed_start~0_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|delayed_start~0_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|delayed_start~0_I .lut_mask = "0000000055555555";

dffeas \acl_work_group_dispatcher:group_dispatcher|delayed_start~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|delayed_start~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|started~0 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|delayed_start ));
defparam \acl_work_group_dispatcher:group_dispatcher|delayed_start~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|delayed_start~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|valid_out[0]~I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__delayed_start ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__dispatched_all_groups~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__full_dff ),
	.combout(\acl_work_group_dispatcher:group_dispatcher|valid_out[0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|valid_out[0]~I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|valid_out[0]~I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|valid_out[0]~I .lut_mask = "CFCFCFCFFFFFFFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0_I .lut_mask = "FCFFFCFF02FE02FE";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "F000FF0FA101FB5B";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~1 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "00015657A8A9FEFF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0_I .lut_mask = "AAAAAAAAAAAAAAAA";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .created_from = "Q(wrreq_delaya[1])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2_I .lut_mask = "0000F0FF0000CCF0";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0_I .lut_mask = "0F0FFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready~I .lut_mask = "FFFFFFFFF5F5F5F5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_var__output_regs_ready ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0_I .lut_mask = "FFFFFFFF05050F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(branch_node_valid_out_0_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~DUPLICATE_I .created_from = "Q(valid_allow[4])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[3] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~34 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~38 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~37_I .lut_mask = "0000FFFF0000AAAA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~2 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~1_I .lut_mask = "0000FCFC000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__accept_inc_bin[0] ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~1 ),
	.cin(gnd),
	.sharein(gnd),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~2 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~3 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~1_I .lut_mask = "0000F0FF00000FF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10_I (
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~10_I .lut_mask = "30303030F0F0F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[0]~1 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[0]~10 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__LessThan1~0 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1_I .lut_mask = "0C0C0C000C0C0C08";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[0]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[1] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~2 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~30 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~29_I .lut_mask = "0000FFFF0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~29 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~2 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[0]~3 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~30 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~31 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~29_I .lut_mask = "000000FF0000FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[3]~11 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[1]~29 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9_I .lut_mask = "FB330033F3330033";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[1]~9 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[2] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~30 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~34 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~33_I .lut_mask = "0000FFFF0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33_I (
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~33 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~30 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[1]~31 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~34 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~35 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~33_I .lut_mask = "000033330000CCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~37 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~34 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[2]~35 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~38 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~39 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~37_I .lut_mask = "00000F0F0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~38 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~22 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21_I (
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~21 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~38 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[3]~39 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~22 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~23 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~21_I .lut_mask = "000033330000CCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[3]~37 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[4]~21 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[2]~33 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[0]~1 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[1]~29 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[5]~25 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|LessThan1~0_I .lut_mask = "CCCCCCC800000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11_I (
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__LessThan1~0 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~11_I .lut_mask = "3333333300000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[3]~11 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[2]~33 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8_I .lut_mask = "CF8F8F8F03030303";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[2]~8 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[5] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~22 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~26 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~25_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~25 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~22 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[4]~23 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~26 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~27 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~25_I .lut_mask = "00000F0F0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[5]~25 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5_I .lut_mask = "00000000C888CCCC";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[5]~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[6] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~26 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~18 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~17_I .lut_mask = "0000FFFF0000FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~17 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~26 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[5]~27 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~18 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~19 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~17_I .lut_mask = "00000F0F0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4_I .lut_mask = "C800C800FF33FF33";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[6]~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[7] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~18 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~14 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~13_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~13 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~18 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[6]~19 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~14 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~15 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~13_I .lut_mask = "000000FF0000FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next[3]~11 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[3]~37 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7_I .lut_mask = "C8FF88FF00330033";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[3]~7 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1_I (
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[3] ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[1] ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[2] ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~1_I .lut_mask = "0000000003030303";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_stalled_by_successors ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0_I .lut_mask = "FFFFFFFF3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready~I .lut_mask = "FFFFFFFFF0F0F000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_var__output_regs_ready ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0_I .lut_mask = "FFFFFFFF00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_node_valid_out_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(branch_node_valid_out_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0_I .lut_mask = "F1F1F1F100000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0_I .lut_mask = "FAFAFAFA00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(merge_node_valid_in_1_staging_reg_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|accept_inc_bin[0]~I .lut_mask = "00AA00AA00A000A0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__valid_out_0 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__accept_inc_bin[0] ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next~0_I .lut_mask = "00000000FF00FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3_I .lut_mask = "00000000B0B0B0B0";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[7]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[8] ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~14 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~10 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~9_I .lut_mask = "0000FFFF0000FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5_I (
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~10 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Add0~5_I .lut_mask = "0000FFFF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9_I (
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~9 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~14 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[7]~15 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9 ),
	.cout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~10 ),
	.shareout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~11 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~9_I .lut_mask = "00000F0F0000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5_I (
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Add0~5 ),
	.cin(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~10 ),
	.sharein(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[8]~11 ),
	.sumout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow_wire[9]~5_I .lut_mask = "000000000000FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2_I .lut_mask = "AA00AA00AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[8]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[8]~9 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[9]~5 ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[7]~13 ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[6]~17 ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__counter_next~0 ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow_wire[4]~21 ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6_I .lut_mask = "00000000C888CCCC";

dffeas \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|counter_next[4]~6 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4] ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|valid_allow[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[4] ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[7] ),
	.datac(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[6] ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[5] ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[0] ),
	.dataf(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__valid_allow[8] ),
	.combout(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|Equal0~0_I .lut_mask = "0000000008000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors~I (
	.dataa(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors~I .lut_mask = "FFFFFFFFFEF0FEF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_stalled_by_successors ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0_I .lut_mask = "33FF33FF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_node_valid_in_staging_reg_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|issue~0_I (
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.combout(\acl_id_iterator:id_iter_inst0|issue~0 ));
defparam \acl_id_iterator:id_iter_inst0|issue~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|issue~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|issue~0_I .lut_mask = "0000FFFF00000000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0_I (
	.dataa(__ALT_INV__start_NO_SHIFT_REG),
	.datad(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0 ));
defparam \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0_I .lut_mask = "00AAAAAA0000AA00";

dffeas \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|just_seen_last_in_group~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|just_seen_last_in_group ));
defparam \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|just_seen_last_in_group~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~1_I .lut_mask = "00000000555F555F";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~0_I .lut_mask = "FFFFCCCC33330000";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2_I .lut_mask = "5555555557575757";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~113_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][0] ),
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[0][0] ),
	.cin(gnd),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~113 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~114 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~113_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~113_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~113_I .lut_mask = "0000FF0000003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~113 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][0])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1~I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "5050FAFA5070FAF8";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0 (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0~COMBOUT ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0 .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0 .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0 .lut_mask = "FF00FF00FF00FF00";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5_I .lut_mask = "01000100FF00FF00";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_comb_bita0~COMBOUT ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|_~5 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_egb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "000FF0FF001FE0FF";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~109_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][1] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][1] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~114 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~109 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~110 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~109_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~109_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~109_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~109 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~69_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][2] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][2] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~110 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~69 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~70 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~69_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~69_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~69_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~69 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~1_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][3] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][3] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~70 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~1 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~2 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~1_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~1_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~1_I .lut_mask = "0000FF0000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][4])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~5_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][4]~DUPLICATE ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][4] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~2 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~5 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~6 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~5_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~5_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~5_I .lut_mask = "0000F0F000003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~9_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][5] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][5] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~6 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~9 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~10 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~9_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~9_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~9_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][6])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~13_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][6]~DUPLICATE ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][6] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~10 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~13 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~14 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~13_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~13_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~13_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][7])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~17_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][7]~DUPLICATE ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][7] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~14 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~17 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~18 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~17_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~17_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~17_I .lut_mask = "0000F0F000005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~73_I (
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][8] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][8] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~18 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~73 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~74 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~73_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~73_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~73_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~73 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~57_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][9] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][9] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~74 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~57 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~58 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~57_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~57_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~57_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~57 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][10])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~61_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][10] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][10]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~58 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~61 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~62 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~61_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~61_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~61_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~61 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][11])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~65_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][11] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][11]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~62 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~65 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~66 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~65_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~65_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~65_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~65 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~45_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][12] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][12] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~66 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~45 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~46 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~45_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~45_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~45_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~45 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~49_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][13] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][13] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~46 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~49 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~50 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~49_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~49_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~49_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~49 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][14])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~53_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][14]~DUPLICATE ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][14] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~50 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~53 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~54 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~53_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~53_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~53_I .lut_mask = "0000F0F000003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~53 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~33_I (
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][15] ),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][15] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~54 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~33 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~34 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~33_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~33_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~33_I .lut_mask = "0000FF00000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~33 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~37_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][16] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][16] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~34 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~37 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~38 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~37_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~37_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~37_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~37 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~41_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][17] ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][17] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~38 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~41 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~42 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~41_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~41_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~41_I .lut_mask = "0000F0F000005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~41 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][18])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~21_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][18]~DUPLICATE ),
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[0][18] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~42 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~21 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~22 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~21_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~21_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~21_I .lut_mask = "0000FF0000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~25_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][19] ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][19] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~22 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~25 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~26 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~25_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~25_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~25_I .lut_mask = "0000F0F000005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~29_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][20] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][20] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~26 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~29 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~30 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~29_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~29_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~29_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][20])";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][21])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~89_I (
	.dataa(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][21]~DUPLICATE ),
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[0][21] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~30 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~89 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~90 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~89_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~89_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~89_I .lut_mask = "0000FF0000005555";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~89 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~93_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][22] ),
	.dataf(\__ALT_INV__local_size_NO_SHIFT_REG[0][22] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~90 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~93 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~94 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~93_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~93_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~93_I .lut_mask = "0000FF0000000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~93 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][23])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~97_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][23] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][23]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~94 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~97 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~98 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~97_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~97_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~97_I .lut_mask = "0000CCCC00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~97 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~101_I (
	.datab(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][24] ),
	.datac(\__ALT_INV__local_size_NO_SHIFT_REG[0][24] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~98 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~101 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~102 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~101_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~101_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~101_I .lut_mask = "0000F0F000003333";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~101 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24]~I .is_wysiwyg = "true";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE_I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~DUPLICATE_I .created_from = "Q(global_id_base_out[0][25])";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~105_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][25] ),
	.datad(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][25]~DUPLICATE ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~102 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~105 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~106 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~105_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~105_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~105_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~105 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~77_I (
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][26] ),
	.datad(\__ALT_INV__local_size_NO_SHIFT_REG[0][26] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~106 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~77 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~78 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~77_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~77_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~77_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~77 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~81_I (
	.datab(\__ALT_INV__local_size_NO_SHIFT_REG[0][27] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][27] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~78 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~81 ),
	.cout(\acl_work_group_dispatcher:group_dispatcher|Add6~82 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~81_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~81_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~81_I .lut_mask = "0000CCCC00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~81 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_work_group_dispatcher:group_dispatcher|Add6~85_I (
	.dataa(\__ALT_INV__local_size_NO_SHIFT_REG[0][28] ),
	.datac(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__global_id_base_out[0][28] ),
	.cin(\acl_work_group_dispatcher:group_dispatcher|Add6~82 ),
	.sumout(\acl_work_group_dispatcher:group_dispatcher|Add6~85 ));
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~85_I .shared_arith = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~85_I .extended_lut = "off";
defparam \acl_work_group_dispatcher:group_dispatcher|Add6~85_I .lut_mask = "0000AAAA00000F0F";

dffeas \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_work_group_dispatcher:group_dispatcher|Add6~85 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~0 ),
	.ena(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15]~1 ),
	.q(\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28] ));
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28]~I .power_up = "low";
defparam \acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28]~I .is_wysiwyg = "true";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][0]~DUPLICATE }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[0] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][1] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[1] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][2] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[2] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][3] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[3] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][4] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[4] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][5] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[5] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][6] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[6] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][7] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[7] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][8] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[8] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][9] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[9] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][10] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[10] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][11] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[11] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][12] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[12] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][13] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[13] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][14] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[14] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][15] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[15] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][16] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[16] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][17] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[17] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][18] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[18] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][19] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[19] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][20]~DUPLICATE }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[20] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][21] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[21] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][22] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[22] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][23] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[23] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][24] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[24] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][25] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[25] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][26] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[26] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][27] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[27] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 (
	.portawe(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\acl_work_group_dispatcher:group_dispatcher|global_id_base_out[0][28] }),
	.portaaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[1] ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|cntr_fgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[1]~1 ,
\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|q_b[28] }));
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .logical_ram_name = "acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ALTSYNCRAM";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 4;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 192;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_last_address = 3;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_address_width = 2;
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~5 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~113_I .lut_mask = "00000F0F000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~109_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~69_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~1_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~5_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~9_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~13_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[7] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~17_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~74 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~73_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~74 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~57_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~61_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~65_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~45_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~49_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~53_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(__ALT_INV__start_NO_SHIFT_REG),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__issue~0 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal3~5 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1_I .lut_mask = "0F0FAFAF0F0F8F8F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~DUPLICATE_I .created_from = "Q(global_id[0][8])";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0] ),
	.cin(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~114 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~113_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[0]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0]~DUPLICATE ),
	.cin(gnd),
	.sharein(gnd),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~114 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~115 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~113_I .lut_mask = "0000CCFF000033CC";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~113 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~113 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~113 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28_I .lut_mask = "0505AFAF0055AAFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~28 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][0]~DUPLICATE_I .created_from = "Q(global_id[0][0])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][1] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~114 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~115 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~110 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~111 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~109_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][1] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~114 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~110 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~109_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~109 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~109 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~109 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29_I .lut_mask = "03030505F3F3F5F5";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~29 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~110 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~70 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~DUPLICATE_I .created_from = "Q(global_id[0][2])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[2] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~110 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~111 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~70 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~71 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~69_I .lut_mask = "00000C0C0000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~69 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~69 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~69 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27_I .lut_mask = "04150415AEBFAEBF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~27 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~70 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~1_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[3] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][3] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~70 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~71 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~2 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~1_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~1 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~1 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~1 ),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0_I .lut_mask = "5555333355550F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~0 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][4] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~2 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~3 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~6 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~5_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][4] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~2 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~5_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~5 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~5 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~5 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2_I .lut_mask = "0A1B0A1B4E5F4E5F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~2 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~6 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~9_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[5] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~6 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~7 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~10 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~11 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~9_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~9 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~9 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~9 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3_I .lut_mask = "04150415AEBFAEBF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][5]~DUPLICATE_I .created_from = "Q(global_id[0][5])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[6] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~10 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~11 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~14 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~15 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~13_I .lut_mask = "000000CC0000CC33";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~10 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~13_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~13 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~13 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~13 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4_I .lut_mask = "0A1B0A1B4E5F4E5F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~4 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][6]~DUPLICATE_I .created_from = "Q(global_id[0][6])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[7] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~14 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~15 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~18 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~19 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~17_I .lut_mask = "000000AA0000AA55";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~14 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~17_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~17 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~17 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~17 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5_I .lut_mask = "01230123CDEFCDEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~DUPLICATE_I .created_from = "Q(global_id[0][7])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~18 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~74 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~73_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[8] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~18 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~19 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~74 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~75 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~73_I .lut_mask = "00000C0C0000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~73 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~73 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~73 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18_I .lut_mask = "02130213CEDFCEDF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~18 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][9] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~74 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~75 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~58 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~59 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~57_I .lut_mask = "000050500000A5A5";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][9] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~74 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~58 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~57_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~57 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~57 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~57 ),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15_I .lut_mask = "0F0F11BB0F0F11BB";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~15 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][10] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~58 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~59 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~62 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~63 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~61_I .lut_mask = "000050500000A5A5";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][10] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~58 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~62 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~61_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~61 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~61 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~61 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16_I .lut_mask = "01230123CDEFCDEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~16 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[11] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~62 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~63 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~66 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~67 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~65_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][11] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~62 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~66 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~65_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~65 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~65 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~65 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17_I .lut_mask = "01230123CDEFCDEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~17 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~66 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~46 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~45_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][12] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[12] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~66 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~67 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~46 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~47 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~45_I .lut_mask = "000030300000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~45 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~45 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~45 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12_I .lut_mask = "0C2E0C2E1D3F1D3F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~12 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~46 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~50 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~49_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[13] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][13] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~46 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~47 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~50 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~51 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~49_I .lut_mask = "00000A0A0000A5A5";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~49 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~49 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~49 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13_I .lut_mask = "02130213CEDFCEDF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~13 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~50 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~54 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~53_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][14] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[14] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~50 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~51 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~54 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~55 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~53_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~53 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~53 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~53 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14_I .lut_mask = "0C2E0C2E1D3F1D3F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~14 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~33_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][15] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~54 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~55 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~34 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~35 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~33_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[15] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~54 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~34 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~33_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~33 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~33 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~33 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9_I .lut_mask = "03000333CFCCCFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~9 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~37_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][16] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~34 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~35 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~38 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~39 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~37_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[16] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~34 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~38 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~37_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~37 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~37 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~37 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10_I .lut_mask = "04040707F4F4F7F7";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~10 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][17] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~38 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~39 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~42 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~43 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~41_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~41_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][17] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~38 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~42 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~41_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~41 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~41 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~41 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11_I .lut_mask = "01CD01CD23EF23EF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~11 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[18]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~42 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~43 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~22 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~23 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~21_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[18] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~42 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~21 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~21 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~21 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6_I .lut_mask = "01230123CDEFCDEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~6 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[19] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~22 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~23 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~26 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~27 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~25_I .lut_mask = "00000A0A0000A5A5";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~25_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[19] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~22 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~25_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~25 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~25 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~25 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7_I .lut_mask = "00033303CCCFFFCF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~7 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[20]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~26 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~27 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~30 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~31 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~29_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~29_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[20] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~26 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~30 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~29_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~29 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~29 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~29 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8_I .lut_mask = "01230123CDEFCDEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~8 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~89_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[21]~DUPLICATE ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~30 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~31 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~90 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~91 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~89_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[21] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~30 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~90 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~89_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~89 ),
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~89 ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~89 ),
	.dataf(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22_I .lut_mask = "0000FFFF53535353";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~22 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][21]~21_I (
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][21] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[21] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][21]~21 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][21]~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][21]~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][21]~21_I .lut_mask = "00000F0FF0F0FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0_I .lut_mask = "00000000000A002A";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][21]~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][21]~21 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0_I .lut_mask = "CCCCCCCCCC00CC00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][22] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[22]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~90 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~91 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~94 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~95 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~93_I .lut_mask = "000030300000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~93_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[22] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~90 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~94 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~93_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~93 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~93 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~93 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23_I .lut_mask = "01012323CDCDEFEF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~23 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~97_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~94 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~98 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~97_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[23] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][23] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~94 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~95 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~98 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~99 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~97_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~97 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~97 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~97 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24_I .lut_mask = "0300CFCC0333CFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~24 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~101_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[24] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~98 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~99 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~102 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~103 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~101_I .lut_mask = "00000C0C0000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[24] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~98 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~102 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~101_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~101 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~101 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~101 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25_I .lut_mask = "00300333CCFCCFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~25 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][24]~24_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[24] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][24] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][24]~24 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][24]~24_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][24]~24_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][24]~24_I .lut_mask = "0000CCCC3333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][24]~24 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][24]~24 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add0~93 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(start_NO_SHIFT_REG),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|max_local_id_0[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[25] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~102 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~103 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~106 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~107 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~105_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[25] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~102 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~106 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~105_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~105 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~105 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~105 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26_I .lut_mask = "10101313DCDCDFDF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE_I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~DUPLICATE_I .created_from = "Q(global_id[0][25])";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~78 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~77_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][26] ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~106 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~107 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~78 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~79 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~77_I .lut_mask = "000050500000A5A5";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[26] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~106 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~78 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~77_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~77 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~77 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~77 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19_I .lut_mask = "02130213CEDFCEDF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~19 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81_I (
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~78 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~81_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][27] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[27]~DUPLICATE ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~78 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~79 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~82 ),
	.shareout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~83 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~81_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[27] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~78 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81 ),
	.cout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~82 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~81_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~81 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~81 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~81 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20_I .lut_mask = "02130213CEDFCEDF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~20 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add10~85_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__max_local_id_0[28]~DUPLICATE ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~82 ),
	.sharein(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~83 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85_I .shared_arith = "on";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add9~85_I .lut_mask = "000000000000C3C3";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[28] ),
	.cin(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~82 ),
	.sumout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|Add6~85_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add10~85 ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Equal0~13 ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add9~85 ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__Add6~85 ),
	.combout(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21 ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21_I .lut_mask = "03000333CFCCCFFF";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~21 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][28]~20_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[28] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][28] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][28]~20 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][28]~20_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][28]~20_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][28]~20_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][28]~20 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][28]~20 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0_I .lut_mask = "FF00FF00F000F000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "CCCCCCCC00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "0000AAAAFFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFCCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "0F0F0F0FAF0FAF0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][60] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_stalled_by_successors ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0_I .lut_mask = "F0F0F0F00000F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[28] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[28] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[28] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21_I .lut_mask = "00331D1DCCFF1D1D";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][56] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[24] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25_I .lut_mask = "000F3355FF0F3355";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[23] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][55] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][23]~23_I (
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[23] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][23] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][23]~23 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][23]~23_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][23]~23_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][23]~23_I .lut_mask = "0000F0F00F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][23]~23 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][23]~23 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[23] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[23] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24_I .lut_mask = "00275527AA27FF27";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~24 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][54] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][22]~22_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][22] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[22] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][22]~22 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][22]~22_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][22]~22_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][22]~22_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][22]~22 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][22]~22 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[22] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[22] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23_I .lut_mask = "00530F53F053FF53";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~23 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][53] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[21] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[21] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22_I .lut_mask = "050511BBAFAF11BB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~22 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][34] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][2]~28_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[2] ),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][2]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][2]~28 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][2]~28_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][2]~28_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][2]~28_I .lut_mask = "333300003333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][2]~28 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][2]~28 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29_I .lut_mask = "3030505F3F3F505F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][1]~27_I (
	.datab(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][1] ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[1] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][1]~27 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][1]~27_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][1]~27_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][1]~27_I .lut_mask = "03030303F3F3F3F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][1]~27 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][1]~27 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28_I .lut_mask = "05052277AFAF2277";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~28 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][32] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][0]~26_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][0]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][0]~26 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][0]~26_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][0]~26_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][0]~26_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][0]~26 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][0]~26 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27_I .lut_mask = "20252A2F70757A7F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~27 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "5577FFFF0000AA88";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7_I .lut_mask = "5757575700000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00A800A857FF57FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00A800A857FF57FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "05AF05AF078F078F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00A800A857FF57FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00A800A857FF57FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6_I .lut_mask = "05AF05AF078F078F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00A800A857FF57FF";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][6]~3_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[6] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][6]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][6]~3 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][6]~3_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][6]~3_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][6]~3_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][6]~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][6]~3 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][9]~14_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[9] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][9] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][9]~14 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][9]~14_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][9]~14_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][9]~14_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][9]~14 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][9]~14 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][10]~15_I (
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][10] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[10] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][10]~15 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][10]~15_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][10]~15_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][10]~15_I .lut_mask = "00000F0FF0F0FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][10]~15 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][10]~15 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][12]~11_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[12] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][12] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][12]~11 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][12]~11_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][12]~11_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][12]~11_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][12]~11 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][12]~11 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][15]~8_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][15] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[15] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][15]~8 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][15]~8_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][15]~8_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][15]~8_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][15]~8 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][15]~8 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][16]~9_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[16] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][16] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][16]~9 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][16]~9_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][16]~9_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][16]~9_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][16]~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][16]~9 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][17]~10_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][17] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[17] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][17]~10 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][17]~10_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][17]~10_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][17]~10_I .lut_mask = "00550055AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][17]~10 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][17]~10 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][19]~6_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[19] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][19] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][19]~6 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][19]~6_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][19]~6_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][19]~6_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][19]~6 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][19]~6 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][20]~7_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][20] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[20] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][20]~7 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][20]~7_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][20]~7_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][20]~7_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][20]~7 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][20]~7 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][27]~19_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][27] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[27] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][27]~19 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][27]~19_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][27]~19_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][27]~19_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][27]~19 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][27]~19 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][59] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[27] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[27] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[27] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20_I .lut_mask = "042615378CAE9DBF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~20 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][58] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][26]~18_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][26] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[26] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][26]~18 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][26]~18_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][26]~18_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][26]~18_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][26]~18 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][26]~18 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[26] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19_I .lut_mask = "03440377CF44CF77";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~19 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][52] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[20] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8_I .lut_mask = "000F3355FF0F3355";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~8 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][51] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[19] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[19] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[19] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7_I .lut_mask = "050511BBAFAF11BB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~7 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][50] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][18]~5_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][18] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[18] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][18]~5 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][18]~5_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][18]~5_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][18]~5_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][18]~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][18]~5 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[18] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[18] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6_I .lut_mask = "272700552727AAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[17] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][49] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[17] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11_I .lut_mask = "010D313DC1CDF1FD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~11 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][48] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[16] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10_I .lut_mask = "303F0505303FF5F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~10 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][47] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[15] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9_I .lut_mask = "012389AB4567CDEF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[14] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][46] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][14]~13_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][14] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[14] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][14]~13 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][14]~13_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][14]~13_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][14]~13_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][14]~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][14]~13 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[14] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[14] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14_I .lut_mask = "10131C1FD0D3DCDF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~14 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[13] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][13]~12_I (
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][13] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[13] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][13]~12 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][13]~12_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][13]~12_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][13]~12_I .lut_mask = "00000F0FF0F0FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][13]~12 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][13]~12 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[13] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[13] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13_I .lut_mask = "00530F53F053FF53";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][44] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[12] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12_I .lut_mask = "001BAA1B551BFF1B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~12 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][43] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][11]~16_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[11] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][11] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][11]~16 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][11]~16_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][11]~16_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][11]~16_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][11]~16 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][11]~16 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[11] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[11] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17_I .lut_mask = "110A115FBB0ABB5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[10] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][42] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[10] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16_I .lut_mask = "010B515BA1ABF1FB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~16 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[9] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15_I .lut_mask = "010D313DC1CDF1FD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~15 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][40] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][8]~17_I (
	.dataa(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[8] ),
	.datac(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][8]~DUPLICATE ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][8]~17 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][8]~17_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][8]~17_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][8]~17_I .lut_mask = "505050505F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][8]~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][8]~17 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[8] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18_I .lut_mask = "04340737C4F4C7F7";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~18 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~5 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][7]~4_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][7] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][7]~4 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][7]~4_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][7]~4_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][7]~4_I .lut_mask = "03CF03CF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][7]~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][7]~4 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[7] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5_I .lut_mask = "505003F35F5F03F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][38] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4_I .lut_mask = "111103CFDDDD03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][37] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][5]~2_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][5]~DUPLICATE ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[5] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][5]~2 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][5]~2_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][5]~2_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][5]~2_I .lut_mask = "00550055AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][5]~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][5]~2 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3_I .lut_mask = "220A225F770A775F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][36] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][4]~1_I (
	.dataa(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datac(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][4] ),
	.datad(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[4] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][4]~1 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][4]~1_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][4]~1_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][4]~1_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][4]~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][4]~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2_I .lut_mask = "04073437C4C7F4F7";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][35] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][3]~0_I (
	.datac(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[3] ),
	.datae(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][3] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][3]~0 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][3]~0_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][3]~0_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][3]~0_I .lut_mask = "0F0F00000F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][3]~0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][3]~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1_I .lut_mask = "5500330F55FF330F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[138]~7_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[138]~7 ));
defparam \kernel_arguments_NO_SHIFT_REG[138]~7_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[138]~7_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[138]~7_I .lut_mask = "0000000000000010";

dffeas \kernel_arguments_NO_SHIFT_REG[138]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[138] ));
defparam \kernel_arguments_NO_SHIFT_REG[138]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[138]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[138] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[8] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21_I .lut_mask = "0000AAAA00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[139]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[11]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[139] ));
defparam \kernel_arguments_NO_SHIFT_REG[139]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[139]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[9] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[139] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13_I .lut_mask = "0000F0F0000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[140]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[12]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[140] ));
defparam \kernel_arguments_NO_SHIFT_REG[140]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[140]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[140] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17_I .lut_mask = "0000CCCC00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[141]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[141] ));
defparam \kernel_arguments_NO_SHIFT_REG[141]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[141]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[141] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5_I .lut_mask = "0000F0F0000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[142]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[14]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[142] ));
defparam \kernel_arguments_NO_SHIFT_REG[142]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[142]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[142] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9_I .lut_mask = "0000CCCC00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[143]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[15]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[138]~7 ),
	.q(\kernel_arguments_NO_SHIFT_REG[143] ));
defparam \kernel_arguments_NO_SHIFT_REG[143]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[143]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[13] ),
	.dataf(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[143] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33_I .lut_mask = "0000FF0000000F0F";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[144]~6_I (
	.dataa(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[144]~6 ));
defparam \kernel_arguments_NO_SHIFT_REG[144]~6_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[144]~6_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[144]~6_I .lut_mask = "0000000100000000";

dffeas \kernel_arguments_NO_SHIFT_REG[144]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[16]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[144] ));
defparam \kernel_arguments_NO_SHIFT_REG[144]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[144]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[14] ),
	.dataf(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[144] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37_I .lut_mask = "0000FF0000000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[145]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[145] ));
defparam \kernel_arguments_NO_SHIFT_REG[145]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[145]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[145] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41_I .lut_mask = "0000FF0000005555";

dffeas \kernel_arguments_NO_SHIFT_REG[146]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[18]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[146] ));
defparam \kernel_arguments_NO_SHIFT_REG[146]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[146]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[16] ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[146] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25_I .lut_mask = "0000F0F000003333";

dffeas \kernel_arguments_NO_SHIFT_REG[147]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[19]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[147] ));
defparam \kernel_arguments_NO_SHIFT_REG[147]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[147]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[147] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[17] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29_I .lut_mask = "0000AAAA00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~6 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE_I .created_from = "Q(local_lvm_input_global_id_0_NO_SHIFT_REG[18])";

dffeas \kernel_arguments_NO_SHIFT_REG[148]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[20]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[148] ));
defparam \kernel_arguments_NO_SHIFT_REG[148]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[148]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[148] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1_I .lut_mask = "0000F0F000005555";

dffeas \kernel_arguments_NO_SHIFT_REG[149]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[21]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[149] ));
defparam \kernel_arguments_NO_SHIFT_REG[149]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[149]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[19] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[149] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61_I .lut_mask = "0000F0F0000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[150]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[22]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[150] ));
defparam \kernel_arguments_NO_SHIFT_REG[150]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[150]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[150] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[20] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65_I .lut_mask = "0000CCCC00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[151]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[23]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[144]~6 ),
	.q(\kernel_arguments_NO_SHIFT_REG[151] ));
defparam \kernel_arguments_NO_SHIFT_REG[151]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[151]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21] ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[151] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53_I .lut_mask = "0000F0F000005555";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[152]~8_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[152]~8 ));
defparam \kernel_arguments_NO_SHIFT_REG[152]~8_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[152]~8_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[152]~8_I .lut_mask = "0000000100000000";

dffeas \kernel_arguments_NO_SHIFT_REG[152]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[24]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[152] ));
defparam \kernel_arguments_NO_SHIFT_REG[152]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[152]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[152] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57_I .lut_mask = "0000CCCC000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[153]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[25]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[153] ));
defparam \kernel_arguments_NO_SHIFT_REG[153]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[153]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[23] ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[153] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45_I .lut_mask = "0000F0F000005555";

dffeas \kernel_arguments_NO_SHIFT_REG[154]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[26]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[154] ));
defparam \kernel_arguments_NO_SHIFT_REG[154]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[154]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[154] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[24] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49_I .lut_mask = "0000F0F0000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[155]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[27]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[155] ));
defparam \kernel_arguments_NO_SHIFT_REG[155]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[155]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[155] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77_I .lut_mask = "0000AAAA00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[156]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[28]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[156] ));
defparam \kernel_arguments_NO_SHIFT_REG[156]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[156]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[156] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81_I .lut_mask = "0000F0F0000000FF";

dffeas \kernel_arguments_NO_SHIFT_REG[157]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[29]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[157] ));
defparam \kernel_arguments_NO_SHIFT_REG[157]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[157]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[157] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69_I .lut_mask = "0000AAAA00000F0F";

dffeas \kernel_arguments_NO_SHIFT_REG[158]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[30]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[152]~8 ),
	.q(\kernel_arguments_NO_SHIFT_REG[158] ));
defparam \kernel_arguments_NO_SHIFT_REG[158]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[158]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[158] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73_I .lut_mask = "0000CCCC000000FF";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~21 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~13 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~17 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~5 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~9 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~33 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~37 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~41 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~25 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~29 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~1 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~61 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~65 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~53 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~57 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~45 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~49 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~77 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~81 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~69 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add2~73 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "BBBBBBBB00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFF3F3F3F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "0CFF0CFF0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0_I .lut_mask = "0C0C0C0C3F3F3F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__o_stall ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_inputs_ready~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0_I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE_I .created_from = "Q(reg_lsu_i_address[8])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0_I .lut_mask = "F7F3FFFFF0F0FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~DUPLICATE ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[8]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Equal1~0_I .lut_mask = "0F0F0F0FF0F0F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~29_I .lut_mask = "0000000000000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add2~29 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1_I .lut_mask = "000FF0FF000FF0FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter~1 ),
	.asdata(vcc),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \~GND~I (
	.combout(\~GND ));
defparam \~GND~I .shared_arith = "off";
defparam \~GND~I .extended_lut = "off";
defparam \~GND~I .lut_mask = "0000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__ready ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0_I .lut_mask = "7777777777777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~25 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~21 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~17 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~13 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~9 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~5 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add2~1 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[2]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|thread_counter[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3_I .lut_mask = "00330033CCFFCCFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[7]~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2_I .lut_mask = "333300003333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[6]~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[5] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1_I .lut_mask = "05050505F5F5F5F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE_I .created_from = "Q(reg_lsu_i_address[5])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1_I .lut_mask = "0F0F0F0F3C3C3C3C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[8]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0_I .lut_mask = "00FF00FF05FA05FA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[8]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~1_I .lut_mask = "A5A500000000A5A5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[5]~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2_I .lut_mask = "55555555AAAAAAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add0~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr_p1[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr_p1[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|match_next_page~0_I .lut_mask = "1090909009090909";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__last_page_addr[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~0_I .lut_mask = "8200008241000041";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Equal1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~1_I .lut_mask = "0000000C0088008C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_page_done~0_I .lut_mask = "0000000031113131";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33_I .lut_mask = "0000FF00000000C4";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~33 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "0F5FFFFF0000F0A0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7_I .lut_mask = "00000F00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00C800C837FF37FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00C800C837FF37FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "03CF03CF078F078F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00C800C837FF37FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_igb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5_I .lut_mask = "0000F0A00F5FFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29_I .lut_mask = "0000FFFF000000C4";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~29 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~25 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~21 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~17 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~13 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~9 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5_I .lut_mask = "0000FFFF0000008C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_page_done~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__next_counter[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1_I .lut_mask = "0000FFFF000000C4";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add5~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|next_counter[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_jgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_last_address = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_address_width = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "F5F5F5F500000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFDDDDDDDD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "0AFF0AFF0A0A0A0A";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[8] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[6] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .created_from = "Q(data[0][6])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[6] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[4] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .created_from = "Q(data[0][4])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[4] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE_I .created_from = "Q(data[0][2])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|q_b[1] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|altsyncram_fen1:FIFOram|__ALT_INV__q_b[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38_I (
	.cin(gnd),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38_I .lut_mask = "000000000000FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~33_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~33 ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~69_I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.cin(gnd),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74_I .lut_mask = "0000000000003330";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~69 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65_I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~65 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~29_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~29 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~61_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~61 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57_I .lut_mask = "0000000000000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~57 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~25_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~25 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~53_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~53 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49_I .lut_mask = "0000000000000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~49 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~21_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~21 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~45_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~45 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41_I .lut_mask = "0000000000003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~41 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~17_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~17 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~37_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~37 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33_I .lut_mask = "0000000000000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~33 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~13_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~13 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~29_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~29 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25_I .lut_mask = "0000000000003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~25 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~9_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~9 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~21 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17_I .lut_mask = "0000000000005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~17 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~5_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~5 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~13_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~13 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9_I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~9 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_writeack~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add7~1_I .lut_mask = "0000FF000000FDEC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add7~1 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~5_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Add10~5 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1_I .lut_mask = "0000000000005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add10~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ack_counter[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0_I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1_I .lut_mask = "55555555FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_exitcond_stall_in~I .lut_mask = "00000F0D0000FFDD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~1_I .lut_mask = "0F0F0F0F05050505";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8_I .lut_mask = "0F0FF0F00F0F3C3C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00003333000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~2_I .lut_mask = "0000080000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~6_I .lut_mask = "0000000080808080";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~6 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "000AA5AF505AF5FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~5 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7_I .lut_mask = "00FF00F000FC000C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~7 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3_I .lut_mask = "5AFF5AFF0AAF0AAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "26BF26BF049D049D";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6_I .lut_mask = "00CCFF3300FDFF02";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~0_I .lut_mask = "0800080000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita7~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita8 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~4_I .lut_mask = "0000000008000800";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "029B029B46DF46DF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5_I .lut_mask = "0F0C0F0C0E020E02";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "0AC40AC40FC00FC0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "0CFF0CFFC0CFC0CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~0_I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "5050FFFFA0A0F5F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .created_from = "Q(wptr_copy[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|wptr_copy[1]~DUPLICATE_I .created_from = "Q(wptr_copy[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_rreq~0_I .lut_mask = "00CC00CC00EF00EF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_wreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~1_I .lut_mask = "0001000100010001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2_I .lut_mask = "00AA00AA08AA08AA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|full_dff~DUPLICATE_I .created_from = "Q(full_dff)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__always1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1_I .lut_mask = "0000000000FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0_I .lut_mask = "C0C0D5D5C000D555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_1_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq~I .lut_mask = "0F0F0F0F00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~0_I .lut_mask = "FFF0FFF000F000F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[1] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~1_I .lut_mask = "00000000555F555F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2_I .lut_mask = "0F0F0F0F3F3F3F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[0] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|__ALT_INV__counter_reg_bit[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita7~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_comb_bita8 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FFFF0000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "30FC30FC70F870F8";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7_I .lut_mask = "3030303030F030F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7_I .lut_mask = "03CF03CF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|_~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|low_addressa[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_lgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__low_addressa[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8_I .lut_mask = "03CF03CF078F078F";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[8] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|cntr_mgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[8]~8 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 512;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_last_address = 511;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_address_width = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "CCCCCCCC00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFF0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_exitcond_stall_in ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "00CC0000F5FDF5F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[9] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~13 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[9] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~17 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[8] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~21 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[7] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[6] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~DUPLICATE_I .created_from = "Q(data[0][6])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[6] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[5] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~25 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[4] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[3] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~29 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[3] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|__ALT_INV__q_b[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~33 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[2] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[1] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~37 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_t_01_0_staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_t_01_0_staging_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_bb1_inc_0_reg_NO_SHIFT_REG[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_t_01_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|data[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_331to332_t_01_0_reg_332_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0_I .lut_mask = "F0F0F0F0F0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9_I (
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9_I .lut_mask = "0000FFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~9 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~0_I .lut_mask = "00000000000C000C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~1_I .lut_mask = "0A000A0000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add3~1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2_I .lut_mask = "0000000000020002";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal0~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_compare_result_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_compare_result_NO_SHIFT_REG ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__branch_node_valid_out_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_0_staging_reg_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|always1~0_I .lut_mask = "DDDDDDDD00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__always1~0 ),
	.datab(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_in_1_staging_reg_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|acl_loop_limiter:loop_limiter_0|__ALT_INV__Equal0~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__branch_node_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_block_selector_NO_SHIFT_REG~0_I .lut_mask = "0505050555455545";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|altsyncram_9kn1:FIFOram|q_b[25] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rcnode_332to333_rc0_bb1_inc_0_reg_333_fifo|acl_ll_fifo:fifo|data[0][57] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_0_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id~26 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][18]~1 ),
	.q(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25] ));
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~I .power_up = "low";
defparam \acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|global_id[0][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_id_iterator:id_iter_inst0|global_id[0][25]~25_I (
	.datab(\acl_id_iterator:id_iter_inst0|__ALT_INV__just_seen_last_in_group ),
	.datae(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|altsyncram_1hn1:FIFOram|__ALT_INV__q_b[25] ),
	.dataf(\acl_id_iterator:id_iter_inst0|acl_work_item_iterator:work_item_iterator|__ALT_INV__global_id[0][25] ),
	.combout(\acl_id_iterator:id_iter_inst0|global_id[0][25]~25 ));
defparam \acl_id_iterator:id_iter_inst0|global_id[0][25]~25_I .shared_arith = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][25]~25_I .extended_lut = "off";
defparam \acl_id_iterator:id_iter_inst0|global_id[0][25]~25_I .lut_mask = "0000CCCC3333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_id_iterator:id_iter_inst0|global_id[0][25]~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[24]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|input_global_id_0_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__input_global_id_0_staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~feeder ),
	.asdata(\acl_id_iterator:id_iter_inst0|global_id[0][25]~25 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__merge_node_valid_in_staging_reg_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|branch_var__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|lvb_input_global_id_0_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[8]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|input_global_id_0_1_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_block_selector_NO_SHIFT_REG~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_0_staging_reg_NO_SHIFT_REG[25] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_0:float_add_basic_block_0|__ALT_INV__lvb_input_global_id_0_reg_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__lvb_input_global_id_0_0_reg_NO_SHIFT_REG[25] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__input_global_id_0_1_staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26_I .lut_mask = "222205AF777705AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG~26 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_stalled_by_successors ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[91]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[27]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[91]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[91]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[91]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[91]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[88]~5_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[1]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[88]~5 ));
defparam \kernel_arguments_NO_SHIFT_REG[88]~5_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[88]~5_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[88]~5_I .lut_mask = "0000000100000000";

dffeas \kernel_arguments_NO_SHIFT_REG[91]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[91]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[91] ));
defparam \kernel_arguments_NO_SHIFT_REG[91]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[91]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[90]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[26]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[90] ));
defparam \kernel_arguments_NO_SHIFT_REG[90]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[90]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[89]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[25]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[89] ));
defparam \kernel_arguments_NO_SHIFT_REG[89]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[89]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[88]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[24]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[88] ));
defparam \kernel_arguments_NO_SHIFT_REG[88]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[87]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[23]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[87]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[87]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[87]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[87]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[80]~3_I (
	.dataa(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_write~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[1]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[80]~3 ));
defparam \kernel_arguments_NO_SHIFT_REG[80]~3_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[80]~3_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[80]~3_I .lut_mask = "0000000100000000";

dffeas \kernel_arguments_NO_SHIFT_REG[87]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[87]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[87] ));
defparam \kernel_arguments_NO_SHIFT_REG[87]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[87]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[86]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[22]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[86] ));
defparam \kernel_arguments_NO_SHIFT_REG[86]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[86]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[85]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[21]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[85]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[85]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[85]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[85]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[85]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[85] ));
defparam \kernel_arguments_NO_SHIFT_REG[85]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[85]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[84]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[20]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[84]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[84]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[84]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[84]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[84]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[84] ));
defparam \kernel_arguments_NO_SHIFT_REG[84]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[84]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[83]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[19]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[83] ));
defparam \kernel_arguments_NO_SHIFT_REG[83]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[83]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[82]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[18]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[82]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[82]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[82]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[82]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[82]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[82]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[82] ));
defparam \kernel_arguments_NO_SHIFT_REG[82]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[82]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[81]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[81] ));
defparam \kernel_arguments_NO_SHIFT_REG[81]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[80]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[16]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[80]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[80]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[80]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[80]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[80]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[80]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[80]~3 ),
	.q(\kernel_arguments_NO_SHIFT_REG[80] ));
defparam \kernel_arguments_NO_SHIFT_REG[80]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[79]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[15]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[79]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[79]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[79]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[79]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[74]~4_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[3]~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[74]~4 ));
defparam \kernel_arguments_NO_SHIFT_REG[74]~4_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[74]~4_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[74]~4_I .lut_mask = "0000000000000004";

dffeas \kernel_arguments_NO_SHIFT_REG[79]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[79]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[79] ));
defparam \kernel_arguments_NO_SHIFT_REG[79]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[79]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[78]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[14]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[78]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[78]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[78]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[78]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[78]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[78] ));
defparam \kernel_arguments_NO_SHIFT_REG[78]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[78]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[77]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[77] ));
defparam \kernel_arguments_NO_SHIFT_REG[77]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[77]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[76]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[12]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[76]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[76]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[76]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[76]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[76]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[76] ));
defparam \kernel_arguments_NO_SHIFT_REG[76]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[75]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[11]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[75]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[75]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[75]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[75]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[75]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[75] ));
defparam \kernel_arguments_NO_SHIFT_REG[75]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[75]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[74]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[74]~4 ),
	.q(\kernel_arguments_NO_SHIFT_REG[74] ));
defparam \kernel_arguments_NO_SHIFT_REG[74]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[74]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[8] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[74] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[9] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[75] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[10] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[76] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[77] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[78] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[13] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[79] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29_I .lut_mask = "0000AAAA000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[80] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[81] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[82] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[16] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[83] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[17] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[84] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[85] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[20] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[86] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[87] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65_I .lut_mask = "0000AAAA00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[88] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[89] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[23] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73_I .lut_mask = "0000AAAA00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[24] ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[90] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77_I .lut_mask = "0000F0F000003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[25] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[91] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81_I .lut_mask = "0000F0F0000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~81 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~77 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[92]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[28]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[92]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[92]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[92]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[92]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[92]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[92] ));
defparam \kernel_arguments_NO_SHIFT_REG[92]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[92]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[92] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53_I .lut_mask = "0000CCCC00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~53 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[94]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[30]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[94]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[94]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[94]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[94]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[94]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[94] ));
defparam \kernel_arguments_NO_SHIFT_REG[94]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[93]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[29]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[93]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[93]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[93]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[93]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[93]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[93]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[88]~5 ),
	.q(\kernel_arguments_NO_SHIFT_REG[93] ));
defparam \kernel_arguments_NO_SHIFT_REG[93]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[93]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[93] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57_I .lut_mask = "0000FF0000005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[94] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61_I .lut_mask = "0000CCCC00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~61 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~57 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .lut_mask = "C00CC00C30033003";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~69 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~73 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE_I .created_from = "Q(o_data[23])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .lut_mask = "8400210000840021";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .lut_mask = "0000000004010401";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .lut_mask = "8008400420021001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~37 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~45 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~41 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .lut_mask = "9000090000900009";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~49 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~DUPLICATE_I .created_from = "Q(o_data[8])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .lut_mask = "8040201008040201";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~25 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~29 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~33 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .lut_mask = "8400008421000021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~5 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~9 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .lut_mask = "8040201008040201";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~21 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~17 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~13 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .lut_mask = "8020401008020401";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .lut_mask = "0000FF0000000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .lut_mask = "9000009009000009";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .lut_mask = "0040004000100010";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .lut_mask = "8400008421000021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .lut_mask = "1090090990900909";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .lut_mask = "8400008421000021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .lut_mask = "8040080420100201";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .lut_mask = "0000000000000001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add1~65 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .lut_mask = "9009000000009009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .lut_mask = "8200008241000041";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .lut_mask = "C00CC00C30033003";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .lut_mask = "A500A50000A500A5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .lut_mask = "0000000000000021";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .lut_mask = "0000000000FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .lut_mask = "0000000055555555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

assign \avm_local_bb1_ld__u0_inst0_waitrequest~input0  = avm_local_bb1_ld__u0_inst0_waitrequest;

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .lut_mask = "0033003000220020";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .lut_mask = "0C0C0C0C0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .lut_mask = "3333333330303030";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .lut_mask = "C000C00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .lut_mask = "0050005000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .lut_mask = "4400DD996420FDB9";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .lut_mask = "5A5AFFFF5050F5F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .lut_mask = "0F0FAFAF0F0F0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I (
	.datac(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .lut_mask = "00000F0FFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .lut_mask = "0E0E0E0EF1F1F1F1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datac(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .lut_mask = "0000FFAB0002FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .lut_mask = "F000F00040004000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~DUPLICATE_I .created_from = "Q(time_out_cnt[3])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2_I .lut_mask = "7773777377777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .lut_mask = "00AAAA0000080800";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .lut_mask = "3366336633663366";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .lut_mask = "00000000F400F400";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .lut_mask = "0005000500050005";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .lut_mask = "0000FF0004000C00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0]~DUPLICATE ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .lut_mask = "0000000000003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .lut_mask = "0F550F550F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|R_valid ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~DUPLICATE_I .created_from = "Q(thread_cnt[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .lut_mask = "0FFF0FFF00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .lut_mask = "03FF03FF03FF03FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .lut_mask = "0005000555555555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .lut_mask = "00FF00FFF5FAF5FA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .lut_mask = "00FF00FF05FA05FA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .lut_mask = "0000000050545054";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .lut_mask = "5F0F5F0F5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .created_from = "Q(num_burst[2])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .lut_mask = "00010001FFFEFFFE";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .lut_mask = "0505050500040004";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE_I .created_from = "Q(num_burst[1])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~DUPLICATE_I .created_from = "Q(num_burst[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .lut_mask = "0055550000040400";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .lut_mask = "0000AAAA00020A08";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .lut_mask = "D5D5D5D500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .lut_mask = "000000FFFDFDCCFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .created_from = "Q(valid_burst)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .lut_mask = "FFFF00000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ),
	.asdata(vcc),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .lut_mask = "0F0FF0F00F0FF0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .lut_mask = "0000FFFF5555AAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .lut_mask = "0000FFFF0505FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .lut_mask = "FFFFFFFF0000FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .lut_mask = "AA000000AA000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .lut_mask = "33FF33FF33323332";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .lut_mask = "00000000FFFFFAFA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .lut_mask = "05FF05FF00FA00FA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .created_from = "Q(offset_valid)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .lut_mask = "00000000000F000F";

assign \avm_local_bb1_ld__u0_inst0_readdatavalid~input0  = avm_local_bb1_ld__u0_inst0_readdatavalid;

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datac(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .lut_mask = "0F1E0F1E0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .lut_mask = "8080808000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .lut_mask = "0040004000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1 ),
	.datab(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .lut_mask = "3404F7C73300FFCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .lut_mask = "50AFFFFF00AFAFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\__ALT_INV__avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .lut_mask = "40FF40FF00BB00BB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .lut_mask = "4440444440404040";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00FF00FF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00FA00FA05FF05FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00FF00FF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00FF00FF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00EE00EE11FF11FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .lut_mask = "00EE00EE11FF11FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00EE00EE11FF11FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|c_word_offset[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~DUPLICATE ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .lut_mask = "FFBBFFBBFFBBFFB0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .lut_mask = "5555555555FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_output_regs_ready ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0_I .lut_mask = "F0F0F0F0FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(local_bb1_ld__u0_valid_out_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_combined_valid~I .lut_mask = "0000FFFFFFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_rreq~I .lut_mask = "00000000F0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_valid_bit_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_162_163_0_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_163_164_0_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_164_165_0_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_165_166_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__SFC_1_VALID_165_166_0_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_166_167_0_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|SFC_1_VALID_167_168_0_NO_SHIFT_REG ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|shift_reg~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5_I .lut_mask = "55555555AAAAAAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~3_I .lut_mask = "0000000005050505";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4_I .lut_mask = "00F000F010F010F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__shift_reg ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__full_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq~I .lut_mask = "0F0F0F0F00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_tg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~1_I .lut_mask = "0300030000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "049D049D26BF26BF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0_I .lut_mask = "66FF66FF22BB22BB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_rreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "26BF26BF049D049D";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV___~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2_I .lut_mask = "00EE00EE00B800B8";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__always1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready~I .lut_mask = "FFFFFFFF0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0_I .lut_mask = "5555FFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_combined_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__combined_valid ),
	.cin(gnd),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22_I .lut_mask = "0000FFCF0000FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~1_I .lut_mask = "00000A0A000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1_I .lut_mask = "AAAAAAAA55555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~5_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2_I .lut_mask = "A0A0A0A05F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~9_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~13 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3_I .lut_mask = "9933993333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~13_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add3~17_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~13 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__Add3~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0_I .lut_mask = "807F807F00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|Add4~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|counter[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__combined_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_combined_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|__ALT_INV__counter[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__stall_in~I .lut_mask = "0303030300000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__stall_in ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__combined_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0_I .lut_mask = "00000000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready~I .lut_mask = "FFFFFFFFFFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__output_regs_ready ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0_I .lut_mask = "FFFFFFFF0000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|data_stall~0_I .lut_mask = "00000000000F000F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0_I .lut_mask = "0F0F0F0F3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_valid~DUPLICATE_I .created_from = "Q(o_valid)";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[26]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[26]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[26]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[24]~2_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[1]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[24]~2 ));
defparam \kernel_arguments_NO_SHIFT_REG[24]~2_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[24]~2_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[24]~2_I .lut_mask = "0000000000040000";

dffeas \kernel_arguments_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[26]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[26] ));
defparam \kernel_arguments_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[25]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[25]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[25] ));
defparam \kernel_arguments_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[24]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[24]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[24]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[24]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[24] ));
defparam \kernel_arguments_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[23]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[23]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[23]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[23]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[23]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[23]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[16]~0_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[16]~0 ));
defparam \kernel_arguments_NO_SHIFT_REG[16]~0_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[16]~0_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[16]~0_I .lut_mask = "0000000000100000";

dffeas \kernel_arguments_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[23]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[23] ));
defparam \kernel_arguments_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[22]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[22] ));
defparam \kernel_arguments_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[21]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[21]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[21]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[21]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[21] ));
defparam \kernel_arguments_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[20]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[20]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[20]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[20]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[20] ));
defparam \kernel_arguments_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[19]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[19] ));
defparam \kernel_arguments_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[18]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[18]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[18] ));
defparam \kernel_arguments_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[17]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[17] ));
defparam \kernel_arguments_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[16]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[16]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[16]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[16]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[16]~0 ),
	.q(\kernel_arguments_NO_SHIFT_REG[16] ));
defparam \kernel_arguments_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[15]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[15]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[15]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[10]~1_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.datac(\__ALT_INV__avs_cra_write~input0 ),
	.datad(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[2]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[10]~1 ));
defparam \kernel_arguments_NO_SHIFT_REG[10]~1_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[10]~1_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[10]~1_I .lut_mask = "0000000000020000";

dffeas \kernel_arguments_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[15]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[15] ));
defparam \kernel_arguments_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[14]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[14]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[14]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[14]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[14] ));
defparam \kernel_arguments_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[13]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[13] ));
defparam \kernel_arguments_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[12]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[12]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[12]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[12] ));
defparam \kernel_arguments_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[11]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[11]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[11]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[11] ));
defparam \kernel_arguments_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[10]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[10]~1 ),
	.q(\kernel_arguments_NO_SHIFT_REG[10] ));
defparam \kernel_arguments_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[8] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[10] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[9] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37_I .lut_mask = "0000AAAA000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[13] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25_I .lut_mask = "0000CCCC000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[15] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[13] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29_I .lut_mask = "0000AAAA00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[16] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[17] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[16] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[18] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[17] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[18]~DUPLICATE ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[20] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5_I (
	.datab(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[21] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5_I .lut_mask = "0000CCCC00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[20] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[21] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[23] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69_I (
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[23] ),
	.dataf(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73_I .lut_mask = "0000FF00000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[24] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77_I .lut_mask = "0000F0F0000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~77 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[21]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[27]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[27] ));
defparam \kernel_arguments_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[25] ),
	.datad(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81_I .lut_mask = "0000F0F0000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~81 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[21] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[22] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~9_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[30]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[30]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[30]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[30]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[30] ));
defparam \kernel_arguments_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

dffeas \kernel_arguments_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[29]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[29] ));
defparam \kernel_arguments_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \kernel_arguments_NO_SHIFT_REG[28]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[28]~input0 ),
	.combout(\kernel_arguments_NO_SHIFT_REG[28]~feeder ));
defparam \kernel_arguments_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \kernel_arguments_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \kernel_arguments_NO_SHIFT_REG[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \kernel_arguments_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\kernel_arguments_NO_SHIFT_REG[28]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\kernel_arguments_NO_SHIFT_REG[24]~2 ),
	.q(\kernel_arguments_NO_SHIFT_REG[28] ));
defparam \kernel_arguments_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \kernel_arguments_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[26] ),
	.datac(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53_I .lut_mask = "0000F0F000003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[29] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57_I .lut_mask = "0000AAAA000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61_I (
	.dataa(\__ALT_INV__kernel_arguments_NO_SHIFT_REG[30] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61_I .lut_mask = "0000AAAA00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~61 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~57 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~7_I .lut_mask = "A500A50000A500A5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~53 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~69 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~73 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~65 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~8_I .lut_mask = "8008200240041001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~9 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~7 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~8 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~10_I .lut_mask = "0000101000000101";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE_I .created_from = "Q(o_data[5])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[5] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_lvm_input_global_id_0_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[4] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~4_I .lut_mask = "9000090000900009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~37 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~45 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~41 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[6] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~3_I .lut_mask = "9000090000900009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[7] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[6] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~49 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[5] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~5_I .lut_mask = "8400008421000021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~29 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~33 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~25 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[9] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~2_I .lut_mask = "9000009009000009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~17 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~13 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~21 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[13] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[12] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~1_I .lut_mask = "8020080240100401";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~9 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add0~5 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[15] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~0_I .lut_mask = "8040080420100201";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~4 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~3 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Equal0~11_I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49_I .lut_mask = "0000CCCC000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~86 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~90 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93_I .lut_mask = "0000FFFF00005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~94 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~98 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73_I .lut_mask = "0000FFFF00000F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61_I .lut_mask = "0000FFFF00005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~61 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[24] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[29] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~7_I .lut_mask = "A500A50000A500A5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~57 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~81 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~89 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~85 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[15] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[17] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~9_I .lut_mask = "8400210000840021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~69 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~73 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[26] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[21] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[22] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~8_I .lut_mask = "9009000000009009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~93 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~97 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~10_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~7 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~9 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~8 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~11_I .lut_mask = "0000000400000001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~49 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~5_I .lut_mask = "0421842184218421";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~33 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~2_I .lut_mask = "8020080240100401";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~37 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~45 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~3_I .lut_mask = "8020401008020401";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~1_I .lut_mask = "9000009009000009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add0~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[12] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[19] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[13] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~0_I .lut_mask = "8040201008040201";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[3] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|R_page_addr_next[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~DUPLICATE_I .created_from = "Q(init)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[5] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__R_page_addr_next[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~4_I .lut_mask = "0000000000840084";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~6_I .lut_mask = "0000000000000001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|match_next_wire~I .lut_mask = "0303030303030303";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~DUPLICATE_I .created_from = "Q(valid_burst)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~0_I .lut_mask = "00000E0E00000E00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~I .lut_mask = "0F000F000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~0_I .lut_mask = "03030303030F030F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2_I .lut_mask = "55FF55FF05FA05FA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1_I .lut_mask = "00FF00FF00F000F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~1 ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~1_I .lut_mask = "0F0F0F0F0F5A0F5A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3_I .lut_mask = "0000000044544454";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0_I .lut_mask = "30FF30FF33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~2_I .lut_mask = "0F0F0F0F0F1E0F1E";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4_I .lut_mask = "0405040504040404";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add4~0_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5_I .lut_mask = "000D0D00000C0C00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add4~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1_I .lut_mask = "00008C8C00048C88";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__inst0_waitrequest~input0  = avm_local_bb1_ld__inst0_waitrequest;

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0_I .lut_mask = "3333333322222222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~0_I .lut_mask = "C000C00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~1_I .lut_mask = "0050005000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0_I .lut_mask = "3038F3FB0008C3CB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4_I .lut_mask = "5A5AFFFF0A0AAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2_I .lut_mask = "0F0FCFCF0F0F0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0_I .lut_mask = "00005555FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|avm_read~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5_I .lut_mask = "0000FAFAFFFF0505";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV___~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0_I .lut_mask = "0000FFF30010FFF7";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|dffe_nae~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~25_I .lut_mask = "0000000000003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~25 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2_I .lut_mask = "00300030FF3FFF3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt~2 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|R_valid ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21_I .lut_mask = "0000FFFF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1_I .lut_mask = "50505050FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~21 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~17 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~13 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~9 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~5 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add2~1_I .lut_mask = "0000FFFF00003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add2~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0_I .lut_mask = "05FF05FF05FF05FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~0 ),
	.asdata(\~GND ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|thread_cnt[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3_I .lut_mask = "CC00CC0040004000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2_I .lut_mask = "3F3F3F3F3B3F3B3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~3 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4_I .lut_mask = "4444888800400080";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~1_I .lut_mask = "3333333366666666";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1_I .lut_mask = "000000008A888A88";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt~1 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[0]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add1~0_I .lut_mask = "0000000003030303";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Add1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0_I .lut_mask = "0000CCCC004000C0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|time_out_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__num_burst[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__thread_cnt[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__time_out_cnt[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|reset_cnt~1_I .lut_mask = "A2A2A2A222222222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~11 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__match_next_wire ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0_I .lut_mask = "333322FF232322FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|valid_burst~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1_I .lut_mask = "FFFF00000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~1 ),
	.asdata(vcc),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0_I .lut_mask = "00FF00FFFF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~0 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1_I .lut_mask = "00FF00FF0FF00FF0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|Add3~1 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0_I .lut_mask = "00FF00FF03FF03FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt~0 ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|delay_cnt[3]~DUPLICATE_I .created_from = "Q(delay_cnt[3])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__o_page_addr_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__delay_cnt[3]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~0_I .lut_mask = "FFFFFFFF0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|__ALT_INV__dffe_nae ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~1_I .lut_mask = "C0C0C0C000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__always2~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0_I .lut_mask = "0FFF0FFF0F0E0F0E";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|init~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~10 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__Equal0~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2_I .lut_mask = "00FF00FF00FA00FA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always2~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0_I .lut_mask = "00FF00FF30FC30FC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|rd_ptr_lsb~DUPLICATE_I .created_from = "Q(rd_ptr_lsb)";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_valid~DUPLICATE_I .created_from = "Q(offset_valid)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4_I .lut_mask = "00000000CCC0CC40";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6_I .lut_mask = "00FF00FF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00FF00FF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[0] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_lvm_input_global_id_0_NO_SHIFT_REG[2] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_new_page }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|fifo_din_en ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|c_word_offset[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~0_I .lut_mask = "0000000005050505";

assign \avm_local_bb1_ld__inst0_readdatavalid~input0  = avm_local_bb1_ld__inst0_readdatavalid;

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4_I .lut_mask = "0F0F0F0F0F4B0F4B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~0_I .lut_mask = "C000C00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~1_I .lut_mask = "0040004000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV___~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0_I .lut_mask = "000CF3FFA2A2AEAE";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3_I .lut_mask = "4BFF4BFF0BBF0BBF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2_I .lut_mask = "40FF40FF00BB00BB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__valid_out_NO_SHIFT_REG ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0_I .lut_mask = "FFFFFFFFFFFA3332";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|valid_rreq~I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00003333000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~DUPLICATE_I .created_from = "Q(counter_reg_bit[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~5_I .lut_mask = "0080000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~2_I .lut_mask = "0000000000000080";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1_I .lut_mask = "3333FFFFC0C0F3F3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__valid_rreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|usedw_will_be_1~0_I .lut_mask = "2FBF2FBF0F9F0F9F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3_I .lut_mask = "00000000FFCCFFCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0_I .lut_mask = "3333333333CC33CC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|_~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~0_I .lut_mask = "0000000000000100";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__fifo_din_en ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_stall~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|__ALT_INV__dffe_af ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1_I .lut_mask = "0000FFFB1000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|dffe_af ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|o_stall~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__R_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__o_stall ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_stall~0_I .lut_mask = "FFFFFFFFFFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_stall~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__inputs_ready ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0_I .lut_mask = "00000000AAAAAAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6_I .lut_mask = "0F0F0F0FF0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~0_I .lut_mask = "0200020000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7~I .lut_mask = "00003333000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_comb_bita7 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~1_I .lut_mask = "0000000000110011";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2_I .lut_mask = "00CC00CC0CCC0CCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0_I .lut_mask = "00000000F0F0FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx_RM_staging_valid_NO_SHIFT_REG ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx3_RM_consumed_0_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_1to1_bb1_arrayidx3_RM_staging_valid_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx_RM_consumed_0_NO_SHIFT_REG ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_stall_in_0~I .lut_mask = "AA220A02FF330F03";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_stall_in_0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~1_I .lut_mask = "5555555500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to331_t_01_0_reg_331_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_l6d1:auto_generated|a_dpfifo_f9a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_1_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__is_merge_data_to_local_regs_valid_NO_SHIFT_REG~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~0_I .lut_mask = "FFFFAAAA00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0_I .lut_mask = "00550055CCDDCCDD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(merge_node_valid_out_2_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|valid_wreq~I .lut_mask = "00000000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_comb_bita6 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|cntr_2h7:usedw_counter|__ALT_INV__counter_reg_bit[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~3_I .lut_mask = "0000000001010101";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~3 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4_I .lut_mask = "1111FFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|_~4 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to332_input_global_id_0_0_reg_332_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_m6d1:auto_generated|a_dpfifo_g9a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_2_NO_SHIFT_REG~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2_I .lut_mask = "33333333FBFBFBFB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|merge_node_valid_out_0_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__merge_node_valid_out_0_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_arrayidx5_RM_consumed_0_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__full_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|valid_wreq~I .lut_mask = "0F000F0000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|cntr_1h7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~4_I .lut_mask = "F000F00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~4 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "002299BB04269DBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__valid_wreq ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV___~3 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__wrreq_delaya[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5_I .lut_mask = "00FC00FC00E200E2";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|_~5 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "0FFF0FFF0C3F0C3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .created_from = "Q(wptr_copy[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__always1~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0_I .lut_mask = "0FFF0FFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[20] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4_I .lut_mask = "0000F0F00F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[20]~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[29]~22 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[30]~23 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[27] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[27]~24 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[28] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[28]~25 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[27] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[28] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[27]~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[28]~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~8_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[29] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[30] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[30]~23 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[29]~22 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~9_I .lut_mask = "0000000082418241";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[25] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16_I .lut_mask = "00F000F00FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[25]~16 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17_I .lut_mask = "0F000F000FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[26]~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[24] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[24]~19 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[23] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[23]~18 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[21]~20 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[22]~21 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[21] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[22] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[21]~20 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[22]~21 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~5_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[24]~19 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[23]~18 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~5 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~6_I .lut_mask = "0000000090099009";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[25] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[26]~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[25]~16 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~7_I .lut_mask = "0000000084218421";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12_I .lut_mask = "00F000F00FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[19]~12 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[18] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11_I .lut_mask = "0F0F00000F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[18]~11 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~DUPLICATE_I .created_from = "Q(data[0][16])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[16]~14 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[17] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[17]~15 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[15]~13 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[16] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[17] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[15]~13 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[16]~14 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[17]~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~3_I .lut_mask = "8008400420021001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[18] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[19]~12 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~3 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[18]~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~4_I .lut_mask = "0084008400210021";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[14] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[14]~6 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[13]~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[11] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[11] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7_I .lut_mask = "03030303CFCFCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8_I .lut_mask = "0F000F000FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[11]~7 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[12]~8 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[9] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9_I .lut_mask = "00550055FF55FF55";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[9]~9 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[10] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[10] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10_I .lut_mask = "000F000FFF0FFF0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[10]~10 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[9] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[10] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[10]~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[9]~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~0_I .lut_mask = "C0C00C0C30300303";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[11]~7 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[12]~8 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~1_I .lut_mask = "0000000084218421";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[13]~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[13] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[14]~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~2_I .lut_mask = "00000000A00A5005";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[20] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__o_data[20]~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~9 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~7 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__Equal0~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10_I .lut_mask = "0000000000000009";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|Equal0~10 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_common_burst~DUPLICATE_I .created_from = "Q(reg_common_burst)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Equal1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~2_I .lut_mask = "00550055F0F5F0F5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_req_valid~I .lut_mask = "000033FF000033BF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0_I .lut_mask = "4AEF4AEF44EE44EE";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq~I .lut_mask = "004C004C000C000C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6_I .lut_mask = "0F0F4BC30F0F4B4B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~1_I .lut_mask = "0400040000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "0051A6F70859AEFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_req_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "0505AFAF8805DDAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2_I .lut_mask = "3232323223232020";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "55005500AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "00FFFFFF00AA55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~DUPLICATE_I .created_from = "Q(wptr_copy[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted~I (
	.datab(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted~I .lut_mask = "0000CCCCCCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3_I .lut_mask = "AA55AA5500000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4_I .lut_mask = "2222DDDD00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0_I .lut_mask = "0022FFDD00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1_I .lut_mask = "0002AAA80000AAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|write_accepted ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|burstcounter[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[1] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~1_I .lut_mask = "03030303030F030F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~0_I .lut_mask = "F0FFF0FFF000F000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2_I .lut_mask = "555555555F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0_I .lut_mask = "0F0FF0F00F0FF0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount~0 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell_I .lut_mask = "FFFFFFFF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "555FFFFF0000AAA0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5_I .lut_mask = "444444444C4C4C4C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "01EF01EF0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "05AF05AF078F078F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00A800A857FF57FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00E000E01FFF1FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0_I .lut_mask = "FFFF00000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~0 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE_I .created_from = "Q(burstcount[1])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1_I .lut_mask = "0FF00FF000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~1 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE_I .created_from = "Q(burstcount[2])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2_I .lut_mask = "0033FFCC0000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~2 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__burstcount[2]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3_I .lut_mask = "00FF00FF02FD02FD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add1~3 ),
	.asdata(\~GND ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|last_page_addr~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[5]~DUPLICATE ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[6] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[7] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[8]~0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[8] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[9] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[10] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[11] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[12] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[14] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[15] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[18] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[20] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[22] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[25] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[30] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[0]~_wirecell }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[1]~DUPLICATE }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[2]~DUPLICATE }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|burstcount[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[10] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[11] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[12] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[13] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[14] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[15] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[16] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[17] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[18] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[19] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[20] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[21] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[22] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[23] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[24] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|valid_wreq ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|page_addr[25] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "F5F5F5F500000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFFF55FF55";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "0A0A0A0ACECECECE";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[4]~30_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[3] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[3]~29_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[0] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[0]~26_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[1]~27_I .lut_mask = "0F0F0F0F33333333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[2]~28_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[0]~26 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[1]~27 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[2]~28 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~0_I .lut_mask = "4800120000480012";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[4]~30 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__burstcounter[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_data[3]~29 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Equal0~1_I .lut_mask = "00000000A50000A5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_valid~0_I .lut_mask = "0F0F0F0FFFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__Equal0~1 ),
	.datac(\__ALT_INV__avm_local_bb1_st_c0_exe1_inst0_waitrequest~input0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__o_valid~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .lut_mask = "00000000AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__empty_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .lut_mask = "00000000FFFFF0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~3_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV___~3 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__valid_wreq ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4_I .lut_mask = "3030303030F030F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~DUPLICATE_I .created_from = "Q(full_dff)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|w_fifo_full~I .lut_mask = "0FFF0FFFFFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready~I .lut_mask = "F0F0FCFCFCF0FCFC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|valid~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5_I .lut_mask = "77BB77BB33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[0]~DUPLICATE_I .created_from = "Q(timeout_counter[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2_I .lut_mask = "7777777733333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4_I .lut_mask = "0000F0F0F0F00000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3_I .lut_mask = "00AA00AA0AA00AA0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[2]~DUPLICATE_I .created_from = "Q(timeout_counter[2])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1_I .lut_mask = "00AA00AA02A802A8";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[2]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|Add3~0_I .lut_mask = "0000000000050005";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Add3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0_I .lut_mask = "00CC00CC0CCC0CCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|timeout_counter[4]~DUPLICATE_I .created_from = "Q(timeout_counter[4])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~2_I .lut_mask = "00000000FF00FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__Equal1~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|waiting~3_I .lut_mask = "00000000EEFFEAFA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6_I .lut_mask = "336C333333CC3333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~0_I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~4_I .lut_mask = "0800080000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~4 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "029B029B46DF46DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~3 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5_I .lut_mask = "00FE00FE00C200C2";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|valid_rreq~0_I .lut_mask = "5555555555005500";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|cntr_vg7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~1_I .lut_mask = "0000000001010101";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV___~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2_I .lut_mask = "00CC00CC04CC04CC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.cin(gnd),
	.sharein(gnd),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38_I .lut_mask = "00000C0000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~38 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~39 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~34 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33_I .lut_mask = "0000F5FF00000AF5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~33 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~34 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~35 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~30 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~29 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~30 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~31 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~26 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~25 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~26 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~27 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~22 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~21 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~22 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~23 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~18 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~17 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~18 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~19 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~14 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~13 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~14 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~15 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~10 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~9 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~10 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~11 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~6 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~6 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~7 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1_I .lut_mask = "000000000000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add2~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|_~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|comb~0_I .lut_mask = "0000000080800000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~0_I .lut_mask = "0000000000330033";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0_I .lut_mask = "000050D00000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6_I .lut_mask = "3333399933339999";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~I .lut_mask = "00005555000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4~I .lut_mask = "00000F0F000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~1_I .lut_mask = "0200020000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_1_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0_I .lut_mask = "029B029B46DF46DF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_2~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_2_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0_I .lut_mask = "5AFF5AFF50F550F5";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_is_0_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_0_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|usedw_will_be_1~0_I .lut_mask = "46DF46DF029B029B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_1~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_will_be_2~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2_I .lut_mask = "0E0E0E0E0D080D08";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|empty_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1_I .lut_mask = "FFFFFFFF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0_I .lut_mask = "0F0F0F0FF0F00F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0_I .lut_mask = "55FF55FF505F505F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_copy[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__write_accepted ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0_I .lut_mask = "0000AAAAAAAAAAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|write~0_I .lut_mask = "5555555555005500";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_ug7:usedw_counter|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~3_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV___~3 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wr_page~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4_I .lut_mask = "0000AAAA00AAAAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|full_dff~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall~I .lut_mask = "FFFFFFFF80008000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__o_stall ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0_I .lut_mask = "0FFFEFFF0FFFAFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE_I .created_from = "Q(local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_valid_out_NO_SHIFT_REG~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0_I .lut_mask = "00000F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_st_c0_exe1_inputs_ready~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_valid~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__full_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter[8] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:ack_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_p3d1:auto_generated|a_dpfifo_j6a1:dpfifo|__ALT_INV__full_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|__ALT_INV__full_dff~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_stall~0_I .lut_mask = "8888000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_333to333_bb1_st_c0_exe1_staging_valid_NO_SHIFT_REG~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_st_c0_exe1_valid_out_NO_SHIFT_REG ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ack_counter[8] ),
	.cin(gnd),
	.sharein(gnd),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38_I .lut_mask = "000000FC00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~38 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~39 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~34 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33_I .lut_mask = "0000FAFF000005FA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~33 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~34 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~35 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~30 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~29 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~30 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~31 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~26 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~25 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~26 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~27 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~22 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~21 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~22 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~23 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~18 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~17 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~18 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~19 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~14 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~13 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~14 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~15 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~10 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~9 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~10 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~11 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~6 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5_I .lut_mask = "000000FF0000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__occ_counter_neg[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~6 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~7 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1_I .lut_mask = "000000000000FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|Add3~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|occ_counter_neg[8] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|o_active~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__o_active ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|o_active~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|has_a_lsu_active~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|__ALT_INV__o_active ),
	.combout(\float_add_function:float_add_function_inst0|has_a_lsu_active~feeder ));
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|has_a_lsu_active~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~DUPLICATE_I .created_from = "Q(has_a_lsu_active)";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0_I (
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish_asserted ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0_I .lut_mask = "0000FFFFFFFFFFFF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~0 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|finish_asserted ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish_asserted~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_work_group_dispatcher:group_dispatcher|dispatched_all_groups ),
	.sclr(start_NO_SHIFT_REG),
	.sload(vcc),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[0] ),
	.sclr(start_NO_SHIFT_REG),
	.sload(vcc),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[1] ),
	.sclr(start_NO_SHIFT_REG),
	.sload(vcc),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|pipelined_dispatched_all_groups[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[24]~3_I (
	.dataa(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_write~input0 ),
	.datae(\__ALT_INV__avs_cra_byteenable[7]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[3]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[24]~3 ));
defparam \workgroup_size_NO_SHIFT_REG[24]~3_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[24]~3_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[24]~3_I .lut_mask = "0000001000000000";

dffeas \workgroup_size_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[63]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[31] ));
defparam \workgroup_size_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[30]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[62]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[30]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[30]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[30]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[30]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[30] ));
defparam \workgroup_size_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[29]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[61]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[29]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[29]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[29]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[29]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[29] ));
defparam \workgroup_size_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[28]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[60]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[28]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[28]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[28] ));
defparam \workgroup_size_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[27]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[59]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[27]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[27]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[27]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[27]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[27]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[27] ));
defparam \workgroup_size_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[58]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[26] ));
defparam \workgroup_size_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[25]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[57]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[25]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[25]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[25] ));
defparam \workgroup_size_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[56]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[24]~3 ),
	.q(\workgroup_size_NO_SHIFT_REG[24] ));
defparam \workgroup_size_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[16]~2_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[6]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[3]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[16]~2 ));
defparam \workgroup_size_NO_SHIFT_REG[16]~2_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[16]~2_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[16]~2_I .lut_mask = "0000010000000000";

dffeas \workgroup_size_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[55]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[23] ));
defparam \workgroup_size_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[22]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[54]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[22]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[22]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[22]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[22]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[22] ));
defparam \workgroup_size_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[53]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[21] ));
defparam \workgroup_size_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[20]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[52]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[20]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[20]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[20]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[20]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[20] ));
defparam \workgroup_size_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[51]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[19] ));
defparam \workgroup_size_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[18]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[50]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[18]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[18]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[18] ));
defparam \workgroup_size_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[17]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[49]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[17]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[17]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[17]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[17]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[17] ));
defparam \workgroup_size_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[48]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[16]~2 ),
	.q(\workgroup_size_NO_SHIFT_REG[16] ));
defparam \workgroup_size_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[15]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[47]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[15]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[8]~1_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_write~input0 ),
	.datac(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datad(\__ALT_INV__avs_cra_byteenable[5]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[3]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[8]~1 ));
defparam \workgroup_size_NO_SHIFT_REG[8]~1_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[8]~1_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[8]~1_I .lut_mask = "0000000200000000";

dffeas \workgroup_size_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[15]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[15] ));
defparam \workgroup_size_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[46]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[14] ));
defparam \workgroup_size_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[13]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[45]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[13]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[13]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[13] ));
defparam \workgroup_size_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[12]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[44]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[12]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[12]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[12] ));
defparam \workgroup_size_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[43]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[11] ));
defparam \workgroup_size_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[10]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[42]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[10]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[10]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[10] ));
defparam \workgroup_size_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[41]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[9] ));
defparam \workgroup_size_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[8]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[40]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[8]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[8]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[8]~1 ),
	.q(\workgroup_size_NO_SHIFT_REG[8] ));
defparam \workgroup_size_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[39]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[7]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[0]~0_I (
	.dataa(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_byteenable[4]~input0 ),
	.datad(\__ALT_INV__avs_cra_write~input0 ),
	.datae(\__ALT_INV__avs_cra_address[2]~input0 ),
	.dataf(\__ALT_INV__avs_cra_address[3]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[0]~0 ));
defparam \workgroup_size_NO_SHIFT_REG[0]~0_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[0]~0_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[0]~0_I .lut_mask = "0000000200000000";

dffeas \workgroup_size_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[7]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[7] ));
defparam \workgroup_size_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[38]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[6] ));
defparam \workgroup_size_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[5]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[37]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[5]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[5]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[5] ));
defparam \workgroup_size_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[36]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[4]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[4] ));
defparam \workgroup_size_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[3]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[35]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[3]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[3] ));
defparam \workgroup_size_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[34]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[2]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[2]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[2] ));
defparam \workgroup_size_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \workgroup_size_NO_SHIFT_REG[1]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[33]~input0 ),
	.combout(\workgroup_size_NO_SHIFT_REG[1]~feeder ));
defparam \workgroup_size_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \workgroup_size_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \workgroup_size_NO_SHIFT_REG[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \workgroup_size_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\workgroup_size_NO_SHIFT_REG[1]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[1] ));
defparam \workgroup_size_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \workgroup_size_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[32]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\workgroup_size_NO_SHIFT_REG[0]~0 ),
	.q(\workgroup_size_NO_SHIFT_REG[0] ));
defparam \workgroup_size_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \workgroup_size_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[0] ),
	.cin(gnd),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~6 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5_I .lut_mask = "0000F0F0000000FF";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0_I (
	.datab(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\acl_work_group_dispatcher:group_dispatcher|__ALT_INV__valid_out[0] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0_I .lut_mask = "FFFFFFFF33333333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[1] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~6 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~10 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[2] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~10 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~14 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[3] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~14 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~18 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][4] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[4] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~18 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~22 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~21 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[5] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~22 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][6] ),
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[6] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~2 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~26 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25_I .lut_mask = "0000F0F000005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~25 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[7] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~26 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~30 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][8] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[8] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~30 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~230 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~229 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[9] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][9] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~230 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~234 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~233 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[10] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~234 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~238 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][11] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[11] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~238 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~242 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~241 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][12] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[12] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~242 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~246 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~245 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225_I (
	.dataa(\__ALT_INV__workgroup_size_NO_SHIFT_REG[13] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][13] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~246 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~226 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225_I .lut_mask = "0000AAAA00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~225 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249_I (
	.datab(\__ALT_INV__workgroup_size_NO_SHIFT_REG[14] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][14] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~226 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~250 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~249 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[15] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~250 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~254 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][16] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[16] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~254 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~262 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~261 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][17] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[17] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~262 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~266 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~265 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][18] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[18] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~266 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~270 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~269 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[19] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~270 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~274 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[20] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~274 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~278 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[21] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~278 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~258 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[22] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][22] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~258 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~282 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~281 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23]~DUPLICATE ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[23] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~282 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~286 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~DUPLICATE_I .created_from = "Q(stages[0][23])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][24] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[24] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~286 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~294 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293_I .lut_mask = "0000CCCC000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~293 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][25] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[25] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~294 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~298 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~297 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][26] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[26] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~298 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~302 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~301 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305_I (
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[27] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][27] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~302 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~306 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~305 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28]~DUPLICATE ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[28] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~306 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~310 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~DUPLICATE_I .created_from = "Q(stages[0][28])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289_I (
	.dataa(\__ALT_INV__workgroup_size_NO_SHIFT_REG[29] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][29] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~310 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~290 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~289 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30] ),
	.datac(\__ALT_INV__workgroup_size_NO_SHIFT_REG[30] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~290 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~314 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313_I .lut_mask = "0000F0F000003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][31] ),
	.datad(\__ALT_INV__workgroup_size_NO_SHIFT_REG[31] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~314 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~318 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317_I .lut_mask = "0000AAAA000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~317 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][32] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~318 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~326 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~325 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~326 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~330 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~DUPLICATE_I .created_from = "Q(stages[0][33])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][34] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~330 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~334 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~333 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][35] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~334 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~338 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~337 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][36] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~338 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~342 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~341 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][37] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~342 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~322 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~321 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][37]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~322 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~346 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~DUPLICATE_I .created_from = "Q(stages[0][38])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][39] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~346 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~350 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~349 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][40] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~350 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~358 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~357 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][41] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~358 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~362 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~361 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][42] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~362 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~366 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~365 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~366 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~370 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~DUPLICATE_I .created_from = "Q(stages[0][43])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][44] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~370 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~374 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~373 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][45] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~374 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~354 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~353 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~354 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~378 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~DUPLICATE_I .created_from = "Q(stages[0][46])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][47] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~378 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~382 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~381 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][48] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~382 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~38 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~37 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][48]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][49] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~38 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~42 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~41 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][50] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~42 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~46 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~45 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][51] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~46 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~50 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~49 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][52] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~50 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~54 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~53 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][52]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][53] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~54 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~34 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~33 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][53]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|valid_out_0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|merge_node_valid_out_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_2:float_add_basic_block_2|__ALT_INV__merge_node_valid_out_NO_SHIFT_REG ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_kernel_finish_detector:kernel_finish_detector|kernel_copy_item_exit[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|completed_items_incr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][0] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__completed_items_incr[0] ),
	.cin(gnd),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~6 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5_I .lut_mask = "0000F0F0000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~5 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~6 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~10 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~10 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~14 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~14 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~18 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][4] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~18 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~22 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~21 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~22 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~2 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~26 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~26 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~30 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][8] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~30 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~230 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~229 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~230 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~234 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~234 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~238 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~238 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~242 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~242 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~246 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~246 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~226 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][14] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~226 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~250 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~249 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][15] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~250 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~254 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~253 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][16] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~254 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~262 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~261 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][17] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~262 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~266 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~265 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~266 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~270 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~270 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~274 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~274 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~278 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~278 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~258 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][22] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~258 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~282 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~281 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][23] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~282 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~286 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~285 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~286 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~294 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~294 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~298 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~DUPLICATE_I .created_from = "Q(stages[0][25])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][26] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~298 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~302 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~301 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][27] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~302 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~306 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~305 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~306 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~310 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~DUPLICATE_I .created_from = "Q(stages[0][28])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][29] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~310 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~290 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~289 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][30] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~290 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~314 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~313 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][31] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~314 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~318 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~317 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][32] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~318 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~326 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~325 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~326 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~330 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~DUPLICATE_I .created_from = "Q(stages[0][33])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][34] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~330 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~334 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~333 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][35] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~334 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~338 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~337 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][36] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~338 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~342 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~341 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~342 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~322 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~DUPLICATE_I .created_from = "Q(stages[0][37])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~322 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~346 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~DUPLICATE_I .created_from = "Q(stages[0][38])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][39] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~346 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~350 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~349 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][40] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~350 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~358 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~357 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][41] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~358 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~362 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~361 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][42] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~362 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~366 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~365 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][43] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~366 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~370 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~369 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~370 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~374 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~DUPLICATE_I .created_from = "Q(stages[0][44])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][45] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~374 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~354 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~353 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][46] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~354 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~378 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~377 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][46]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][47] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~378 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~382 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~381 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~382 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~38 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~DUPLICATE_I .created_from = "Q(stages[0][48])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~38 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~42 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~DUPLICATE_I .created_from = "Q(stages[0][49])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][50] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~42 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~46 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~45 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][51] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~46 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~50 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~49 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][52] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~50 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~54 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~53 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][52]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][52] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][51] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][52] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][51] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal6~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~1_I .lut_mask = "C030C0300C030C03";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~37 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][48]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~41 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][49] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][50] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][48] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][48] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][49] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][50] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal6~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~0_I .lut_mask = "8008400420021001";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~DUPLICATE_I .created_from = "Q(stages[0][53])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~54 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~34 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~33 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][54] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~34 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~58 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~57 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][54]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~DUPLICATE_I .created_from = "Q(stages[0][55])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][54] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~34 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~58 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~57 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~58 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~62 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~61 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][55]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~DUPLICATE_I .created_from = "Q(stages[0][55])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~58 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~62 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~61 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][54] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][55] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][55] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][54] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal6~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~2_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal6~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][53] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~1 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~0 ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][53] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal6~2 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal6~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal6~3_I .lut_mask = "0000000002010201";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal6~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][40] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][41] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][42] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][40] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][41] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][42] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal5~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~0_I .lut_mask = "8040201008040201";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~377 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][46]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][46] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][47] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][47] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][46] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal5~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~2_I .lut_mask = "A0A00A0A50500505";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~369 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][43]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~373 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][44] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][43] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][43] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][44] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal5~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~1_I .lut_mask = "C0C00C0C30300303";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal5~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][45] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~0 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][45] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~2 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal5~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal5~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal5~3_I .lut_mask = "0000000000002121";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal5~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[5]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~257 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][21]~DUPLICATE_I .created_from = "Q(stages[0][21])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~257 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][21]~DUPLICATE_I .created_from = "Q(stages[0][21])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~269 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][18]~DUPLICATE_I .created_from = "Q(stages[0][18])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][18]~DUPLICATE ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][17] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][17] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][16] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][18] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][16] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal2~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~0_I .lut_mask = "8200410000820041";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~285 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][23] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][22] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][23] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][22] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal2~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~2_I .lut_mask = "C030C0300C030C03";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~277 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][20]~DUPLICATE_I .created_from = "Q(stages[0][20])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~277 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][20]~DUPLICATE_I .created_from = "Q(stages[0][20])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~273 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][19]~DUPLICATE_I .created_from = "Q(stages[0][19])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~273 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][19]~DUPLICATE_I .created_from = "Q(stages[0][19])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][20]~DUPLICATE ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][20]~DUPLICATE ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][19]~DUPLICATE ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][19]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal2~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~1_I .lut_mask = "A500A50000A500A5";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal2~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][21]~DUPLICATE ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][21]~DUPLICATE ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~0 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~2 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal2~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal2~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal2~3_I .lut_mask = "0000000000000909";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal2~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[2]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~321 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][37]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~345 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][38]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~345 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][38] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][39] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][39] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][38] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal4~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~2_I .lut_mask = "A00AA00A50055005";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~329 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][33]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~329 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][32] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][34] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][33] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][34] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][32] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][33] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal4~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~0_I .lut_mask = "8020401008020401";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][36] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][35] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][36] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][35] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal4~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~1_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal4~3_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][37] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][37] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~2 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~0 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal4~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal4~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal4~3_I .lut_mask = "00000000000000C3";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal4~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[4]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~225 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][13]~DUPLICATE_I .created_from = "Q(stages[0][13])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~241 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][11]~DUPLICATE_I .created_from = "Q(stages[0][11])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~245 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][12]~DUPLICATE_I .created_from = "Q(stages[0][12])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][11]~DUPLICATE ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][12]~DUPLICATE ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][11] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][12] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal1~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~1_I .lut_mask = "C030C0300C030C03";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~253 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][15]~DUPLICATE_I .created_from = "Q(stages[0][15])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][14] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][14] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][15]~DUPLICATE ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][15] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal1~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~2_I .lut_mask = "A500A50000A500A5";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~233 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][9]~DUPLICATE_I .created_from = "Q(stages[0][9])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~237 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][10]~DUPLICATE_I .created_from = "Q(stages[0][10])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~237 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][10]~DUPLICATE_I .created_from = "Q(stages[0][10])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][8] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][8] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][9]~DUPLICATE ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][10]~DUPLICATE ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][9] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][10]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal1~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~0_I .lut_mask = "9000090000900009";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal1~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][13]~DUPLICATE ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][13] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~1 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~2 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal1~0 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal1~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal1~3_I .lut_mask = "0000000000000909";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal1~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[1]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~313 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][30]~DUPLICATE_I .created_from = "Q(stages[0][30])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][30] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][31] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][31] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][30]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal3~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~2_I .lut_mask = "A0A00A0A50500505";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~309 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][28]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~309 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][28] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][27] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][27] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][28] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal3~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~1_I .lut_mask = "C00CC00C30033003";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~297 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][25]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~293 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][24]~DUPLICATE_I .created_from = "Q(stages[0][24])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][25] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][24] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][25] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][24]~DUPLICATE ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][26] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][26] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal3~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~0_I .lut_mask = "8421000000008421";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal3~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~2 ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][29] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][29] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~1 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal3~0 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal3~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal3~3_I .lut_mask = "0000000000004141";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal3~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[5] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[2] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[4] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[1] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[3] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~1_I .lut_mask = "0000000000000003";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~29 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][7]~DUPLICATE_I .created_from = "Q(stages[0][7])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~25 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][6]~DUPLICATE_I .created_from = "Q(stages[0][6])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~29 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][7]~DUPLICATE_I .created_from = "Q(stages[0][7])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][6] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][7]~DUPLICATE ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][6]~DUPLICATE ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][7]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal0~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~2_I .lut_mask = "C030C0300C030C03";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~1 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][5]~DUPLICATE_I .created_from = "Q(stages[0][5])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~17 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][3]~DUPLICATE_I .created_from = "Q(stages[0][3])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~17 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][3]~DUPLICATE_I .created_from = "Q(stages[0][3])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][4] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][4] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][3]~DUPLICATE ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][3]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal0~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~1_I .lut_mask = "A500A50000A500A5";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~13 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][2]~DUPLICATE_I .created_from = "Q(stages[0][2])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~9 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][1]~DUPLICATE_I .created_from = "Q(stages[0][1])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~13 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][2]~DUPLICATE_I .created_from = "Q(stages[0][2])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~5 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][0]~DUPLICATE_I .created_from = "Q(stages[0][0])";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~9 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][1]~DUPLICATE_I .created_from = "Q(stages[0][1])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][2]~DUPLICATE ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][1]~DUPLICATE ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][2]~DUPLICATE ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][0]~DUPLICATE ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][0] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][1]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal0~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~0_I .lut_mask = "8400008421000021";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~1 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][5]~DUPLICATE_I .created_from = "Q(stages[0][5])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal0~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~2 ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][5]~DUPLICATE ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~1 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal0~0 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][5]~DUPLICATE ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal0~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal0~3_I .lut_mask = "0000040400000101";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal0~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[0]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~DUPLICATE_I .created_from = "Q(stages[0][61])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][56] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~62 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~70 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~69 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][57] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~70 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~74 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~73 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][58] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~74 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~78 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~77 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~78 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~82 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~DUPLICATE_I .created_from = "Q(stages[0][59])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][60] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~82 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~86 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~85 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~86 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~66 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~65 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][61]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~DUPLICATE_I .created_from = "Q(stages[0][56])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~62 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~70 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~69 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][57] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~70 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~74 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~73 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][58] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~74 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~78 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~77 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][56] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][57] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][58] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][56] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][58] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][57] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal7~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~0_I .lut_mask = "8040080420100201";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~78 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~82 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~DUPLICATE_I .created_from = "Q(stages[0][59])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~82 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~86 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~DUPLICATE_I .created_from = "Q(stages[0][60])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][61] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~86 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~66 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~65 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][61]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~DUPLICATE_I .created_from = "Q(stages[0][63])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][62] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~66 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~90 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~89 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~90 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~94 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~93 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][62] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~66 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~90 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~89 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][63] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~90 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~94 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~93 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][63]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][63] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][62] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][63] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][62] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal7~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~2_I .lut_mask = "A050A0500A050A05";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~81 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][59]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~85 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][60]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~81 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][59]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][59] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][60] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][60] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][59] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal7~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~1_I .lut_mask = "C00CC00C30033003";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal7~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][61] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~0 ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][61] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~2 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal7~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal7~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal7~3_I .lut_mask = "0000000000000A05";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal7~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[7]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~DUPLICATE_I .created_from = "Q(stages[0][68])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~94 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~102 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~DUPLICATE_I .created_from = "Q(stages[0][64])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][65] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~102 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~106 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~105 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][65]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~106 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~110 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~DUPLICATE_I .created_from = "Q(stages[0][66])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~110 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~114 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~DUPLICATE_I .created_from = "Q(stages[0][67])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~114 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~118 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~117 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][68]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~94 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~102 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~DUPLICATE_I .created_from = "Q(stages[0][64])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][65] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~102 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~106 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~105 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][65]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~106 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~110 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~DUPLICATE_I .created_from = "Q(stages[0][66])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~110 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~114 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~DUPLICATE_I .created_from = "Q(stages[0][67])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][68] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~114 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~118 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~117 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][68]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~113 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][67]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~113 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][67]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][68] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][68] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][67] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][67] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal8~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~1_I .lut_mask = "9090090990900909";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~101 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][64]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~109 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][66]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~109 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][66]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~101 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][64]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][65] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][64] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][65] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][66] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][66] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][64] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal8~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~0_I .lut_mask = "8400008421000021";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~118 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~98 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~DUPLICATE_I .created_from = "Q(stages[0][69])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][70] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~98 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~122 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~121 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][70]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~DUPLICATE_I .created_from = "Q(stages[0][71])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~122 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~126 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~125 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][71]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~DUPLICATE_I .created_from = "Q(stages[0][71])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~118 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~98 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~DUPLICATE_I .created_from = "Q(stages[0][69])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][70] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~98 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~122 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~121 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][70]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~122 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~126 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~125 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][71]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][70] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][71] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][71] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][70] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal8~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~2_I .lut_mask = "A0A00A0A50500505";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~97 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][69]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~97 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][69]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal8~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~1 ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~0 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal8~2 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][69] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][69] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal8~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal8~3_I .lut_mask = "0101000000000101";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal8~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][72] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~126 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~134 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~133 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][72]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~134 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~138 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~DUPLICATE_I .created_from = "Q(stages[0][73])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~138 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~142 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~DUPLICATE_I .created_from = "Q(stages[0][74])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][75] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~142 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~146 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~145 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][75]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~146 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~150 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~DUPLICATE_I .created_from = "Q(stages[0][76])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][77] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~150 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~130 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~129 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][77]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~141 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][74]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~DUPLICATE_I .created_from = "Q(stages[0][73])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~126 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~134 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~DUPLICATE_I .created_from = "Q(stages[0][72])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~134 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~138 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~137 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][73]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~137 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][73]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~133 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][72]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][74] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~138 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~142 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~141 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][74]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][74] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][73] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][73] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][72] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][72] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][74] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal9~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~0_I .lut_mask = "8200008241000041";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][78] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~130 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~154 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~153 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][78]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~DUPLICATE_I .created_from = "Q(stages[0][78])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~142 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~146 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~DUPLICATE_I .created_from = "Q(stages[0][75])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][76] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~146 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~150 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~149 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][77] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~150 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~130 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~129 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][77]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~130 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~154 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~153 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][78]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~DUPLICATE_I .created_from = "Q(stages[0][79])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~154 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~158 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~157 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][79]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][79] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~154 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~158 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~157 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][79]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][78] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][78] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][79] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][79] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal9~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~2_I .lut_mask = "A5A500000000A5A5";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~145 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][75]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~149 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][75] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][76] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][75] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][76] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal9~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~1_I .lut_mask = "C0C030300C0C0303";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal9~3_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][77] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~0 ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~2 ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][77] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal9~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal9~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal9~3_I .lut_mask = "00000000000C0003";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal9~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0_I (
	.dataf(__ALT_INV__start_NO_SHIFT_REG),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[12]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~DUPLICATE_I .created_from = "Q(stages[0][93])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][80] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~158 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~166 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~165 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][81] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~166 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~170 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~169 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][82] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~170 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~174 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~173 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][82]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~174 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~178 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~DUPLICATE_I .created_from = "Q(stages[0][83])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~178 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~182 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~DUPLICATE_I .created_from = "Q(stages[0][84])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~182 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~162 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~DUPLICATE_I .created_from = "Q(stages[0][85])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~162 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~186 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~DUPLICATE_I .created_from = "Q(stages[0][86])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~186 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~190 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~DUPLICATE_I .created_from = "Q(stages[0][87])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][88] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~190 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~198 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~197 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][89] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~198 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~202 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~201 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][89]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][90] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~202 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~206 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~205 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][90]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][91] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~206 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~210 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~209 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][91]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][92] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~210 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~214 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~213 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][92]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~214 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~194 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~193 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][93]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~DUPLICATE_I .created_from = "Q(stages[0][88])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~158 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~166 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~DUPLICATE_I .created_from = "Q(stages[0][80])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169_I (
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][81] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~166 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~170 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169_I .lut_mask = "0000FFFF000000FF";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~169 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][82] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~170 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~174 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~173 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][82]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][83] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~174 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~178 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~177 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][83]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][84] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~178 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~182 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~181 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][84]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][85] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~182 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~162 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~161 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][85]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][86] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~162 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~186 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~185 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][86]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][87] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~186 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~190 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~189 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][87]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~190 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~198 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~197 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][89] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~198 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~202 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~201 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][89]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][90] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~202 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~206 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~205 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][90]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][88] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][89] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][90] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][90] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][89] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][88] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal11~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~0_I .lut_mask = "8008200240041001";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE_I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE_I .is_wysiwyg = "true";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~DUPLICATE_I .created_from = "Q(stages[0][93])";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][91] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~206 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~210 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209_I .lut_mask = "0000FFFF00005555";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~209 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][91]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][92] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~210 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~214 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~213 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][92]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93]~DUPLICATE ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~214 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~194 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~193 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][93]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][94] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~194 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~218 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~217 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][95] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~218 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~221 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][95]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][94] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~194 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217 ),
	.cout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~218 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217_I .lut_mask = "0000FFFF00003333";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~217 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][95] ),
	.cin(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~218 ),
	.sumout(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221_I .lut_mask = "0000FFFF00000F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~221 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][95]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][94] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][95] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][95] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][94] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal11~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~2_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][92] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][91] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][92] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][91] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal11~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~1_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal11~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][93] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~0 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][93] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~2 ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal11~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal11~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal11~3_I .lut_mask = "0000000000002121";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal11~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[11]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~185 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][86]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~189 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][87]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][86] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][87] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][87] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][86] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal10~2 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~2_I .lut_mask = "A00AA00A50055005";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|Add0~165 ),
	.sclr(start_NO_SHIFT_REG),
	.ena(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][63]~0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|stages[0][80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][81] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][82] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][80] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][81] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][82] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][80] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal10~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~0_I .lut_mask = "8040201008040201";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~161 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][85]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~177 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][83]~I .is_wysiwyg = "true";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|Add0~181 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|stages[0][84]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1_I (
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][84] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][83] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][84] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][83] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal10~1 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~1_I .lut_mask = "C030C0300C030C03";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|Equal10~3_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_sum|__ALT_INV__stages[0][85] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~2 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~0 ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|acl_multistage_accumulator:ndrange_completed|__ALT_INV__stages[0][85] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__Equal10~1 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|Equal10~3 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~3_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~3_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|Equal10~3_I .lut_mask = "0000000002010201";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|Equal10~3 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10] ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10]~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|registered_ranges[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0_I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[8] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[9] ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[12] ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[11] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[10] ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~0_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~I (
	.dataa(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[6] ),
	.datab(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~1 ),
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[0] ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__registered_ranges[7] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__WideAnd0~0 ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|WideAnd0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|WideAnd0~I .lut_mask = "0000000000000101";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|WideAnd0 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|cmp_result_reg~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__pipelined_dispatched_all_groups[2] ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__cmp_result_reg ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0_I .lut_mask = "000000000F0F0F0F";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~0 ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(start_NO_SHIFT_REG),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|ndrange_done ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|ndrange_done~I .is_wysiwyg = "true";

cyclonev_lcell_comb \acl_kernel_finish_detector:kernel_finish_detector|finish~0_I (
	.datac(\float_add_function:float_add_function_inst0|__ALT_INV__has_a_lsu_active~DUPLICATE ),
	.datae(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish_asserted ),
	.dataf(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__ndrange_done ),
	.combout(\acl_kernel_finish_detector:kernel_finish_detector|finish~0 ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish~0_I .shared_arith = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish~0_I .extended_lut = "off";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish~0_I .lut_mask = "00000000F0F00000";

dffeas \acl_kernel_finish_detector:kernel_finish_detector|finish~I (
	.clk(\clock~CLKENA0 ),
	.d(\acl_kernel_finish_detector:kernel_finish_detector|finish~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\acl_kernel_finish_detector:kernel_finish_detector|finish ));
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish~I .power_up = "low";
defparam \acl_kernel_finish_detector:kernel_finish_detector|finish~I .is_wysiwyg = "true";

cyclonev_lcell_comb \started_NO_SHIFT_REG~0_I (
	.datac(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish ),
	.datad(__ALT_INV__started_NO_SHIFT_REG),
	.dataf(__ALT_INV__start_NO_SHIFT_REG),
	.combout(\started_NO_SHIFT_REG~0 ));
defparam \started_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \started_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \started_NO_SHIFT_REG~0_I .lut_mask = "00F000F0F0F0F0F0";

dffeas \started_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\started_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\__ALT_INV__avs_cra_write~input0 ),
	.q(started_NO_SHIFT_REG));
defparam \started_NO_SHIFT_REG~I .power_up = "low";
defparam \started_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \start_NO_SHIFT_REG~0_I (
	.datad(__ALT_INV__started_NO_SHIFT_REG),
	.datae(__ALT_INV__start_NO_SHIFT_REG),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[0] ),
	.combout(\start_NO_SHIFT_REG~0 ));
defparam \start_NO_SHIFT_REG~0_I .shared_arith = "off";
defparam \start_NO_SHIFT_REG~0_I .extended_lut = "off";
defparam \start_NO_SHIFT_REG~0_I .lut_mask = "0000FF00FF00FF00";

dffeas \start_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\start_NO_SHIFT_REG~0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\__ALT_INV__avs_cra_write~input0 ),
	.q(start_NO_SHIFT_REG));
defparam \start_NO_SHIFT_REG~I .power_up = "low";
defparam \start_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[3]~1_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_address[0]~input0 ),
	.combout(\status_NO_SHIFT_REG[3]~1 ));
defparam \status_NO_SHIFT_REG[3]~1_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[3]~1_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[3]~1_I .lut_mask = "4000000040000000";

cyclonev_lcell_comb \status_NO_SHIFT_REG[0]~3_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(__ALT_INV__start_NO_SHIFT_REG),
	.datac(\__ALT_INV__status_NO_SHIFT_REG[3]~1 ),
	.datad(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[0] ),
	.dataf(\__ALT_INV__avs_cra_writedata[0]~input0 ),
	.combout(\status_NO_SHIFT_REG[0]~3 ));
defparam \status_NO_SHIFT_REG[0]~3_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[0]~3_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[0]~3_I .lut_mask = "0000D5D00005D5D5";

dffeas \status_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[0]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\status_NO_SHIFT_REG[0] ));
defparam \status_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector31~0_I (
	.datae(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[0] ),
	.combout(\Selector31~0 ));
defparam \Selector31~0_I .shared_arith = "off";
defparam \Selector31~0_I .extended_lut = "off";
defparam \Selector31~0_I .lut_mask = "000000000000FFFF";

dffeas \cra_readdata_st1_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector31~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[0] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \cra_addr_st1_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_address[1]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\cra_addr_st1_NO_SHIFT_REG[1] ));
defparam \cra_addr_st1_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \cra_addr_st1_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \cra_addr_st1_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_address[0]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\cra_addr_st1_NO_SHIFT_REG[0] ));
defparam \cra_addr_st1_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \cra_addr_st1_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \cra_addr_st1_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_address[2]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\cra_addr_st1_NO_SHIFT_REG[2] ));
defparam \cra_addr_st1_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \cra_addr_st1_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \cra_addr_st1_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_address[3]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\cra_addr_st1_NO_SHIFT_REG[3] ));
defparam \cra_addr_st1_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \cra_addr_st1_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Equal0~0_I (
	.dataa(\__ALT_INV__cra_addr_st1_NO_SHIFT_REG[1] ),
	.datac(\__ALT_INV__cra_addr_st1_NO_SHIFT_REG[0] ),
	.datae(\__ALT_INV__cra_addr_st1_NO_SHIFT_REG[2] ),
	.dataf(\__ALT_INV__cra_addr_st1_NO_SHIFT_REG[3] ),
	.combout(\Equal0~0 ));
defparam \Equal0~0_I .shared_arith = "off";
defparam \Equal0~0_I .extended_lut = "off";
defparam \Equal0~0_I .lut_mask = "5050000000000000";

dffeas \avs_cra_readdata[0]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[0] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[0]~reg0 ));
defparam \avs_cra_readdata[0]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[0]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[1]~2_I (
	.dataa(\__ALT_INV__avs_cra_write~input0 ),
	.datab(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.datac(\__ALT_INV__status_NO_SHIFT_REG[3]~1 ),
	.datad(\acl_kernel_finish_detector:kernel_finish_detector|__ALT_INV__finish ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[1] ),
	.dataf(\__ALT_INV__avs_cra_writedata[1]~input0 ),
	.combout(\status_NO_SHIFT_REG[1]~2 ));
defparam \status_NO_SHIFT_REG[1]~2_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[1]~2_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[1]~2_I .lut_mask = "0AAAFEFE0BABFFFF";

dffeas \status_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[1]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\status_NO_SHIFT_REG[1] ));
defparam \status_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector30~0_I (
	.datae(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[1] ),
	.combout(\Selector30~0 ));
defparam \Selector30~0_I .shared_arith = "off";
defparam \Selector30~0_I .extended_lut = "off";
defparam \Selector30~0_I .lut_mask = "000000000000FFFF";

dffeas \cra_readdata_st1_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector30~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[1] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[1]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[1] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[1]~reg0 ));
defparam \avs_cra_readdata[1]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[1]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[3]~0_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[0]~input0 ),
	.combout(\status_NO_SHIFT_REG[3]~0 ));
defparam \status_NO_SHIFT_REG[3]~0_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[3]~0_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[3]~0_I .lut_mask = "0000000000008000";

dffeas \status_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[2]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[2] ));
defparam \status_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector29~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.datac(\__ALT_INV__status_NO_SHIFT_REG[2] ),
	.combout(\Selector29~0 ));
defparam \Selector29~0_I .shared_arith = "off";
defparam \Selector29~0_I .extended_lut = "off";
defparam \Selector29~0_I .lut_mask = "0505050505050505";

dffeas \cra_readdata_st1_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector29~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[2] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[2]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[2] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[2]~reg0 ));
defparam \avs_cra_readdata[2]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[2]~reg0_I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[3]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[3] ));
defparam \status_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector28~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[3] ),
	.combout(\Selector28~0 ));
defparam \Selector28~0_I .shared_arith = "off";
defparam \Selector28~0_I .extended_lut = "off";
defparam \Selector28~0_I .lut_mask = "0000555500005555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector28~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[3] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[3]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[3] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[3]~reg0 ));
defparam \avs_cra_readdata[3]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[3]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[4]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[4]~input0 ),
	.combout(\status_NO_SHIFT_REG[4]~feeder ));
defparam \status_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \status_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[4]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[4] ));
defparam \status_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector27~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[4] ),
	.combout(\Selector27~0 ));
defparam \Selector27~0_I .shared_arith = "off";
defparam \Selector27~0_I .extended_lut = "off";
defparam \Selector27~0_I .lut_mask = "0000000055555555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector27~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[4] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[4]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[4] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[4]~reg0 ));
defparam \avs_cra_readdata[4]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[4]~reg0_I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[5]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[5] ));
defparam \status_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector26~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[5] ),
	.combout(\Selector26~0 ));
defparam \Selector26~0_I .shared_arith = "off";
defparam \Selector26~0_I .extended_lut = "off";
defparam \Selector26~0_I .lut_mask = "0000000055555555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector26~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[5] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[5]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[5] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[5]~reg0 ));
defparam \avs_cra_readdata[5]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[5]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[6]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[6]~input0 ),
	.combout(\status_NO_SHIFT_REG[6]~feeder ));
defparam \status_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \status_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[6]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[6] ));
defparam \status_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector25~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[6] ),
	.combout(\Selector25~0 ));
defparam \Selector25~0_I .shared_arith = "off";
defparam \Selector25~0_I .extended_lut = "off";
defparam \Selector25~0_I .lut_mask = "0000555500005555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector25~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[6] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[6]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[6] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[6]~reg0 ));
defparam \avs_cra_readdata[6]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[6]~reg0_I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[7]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\status_NO_SHIFT_REG[3]~0 ),
	.q(\status_NO_SHIFT_REG[7] ));
defparam \status_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector24~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[7] ),
	.combout(\Selector24~0 ));
defparam \Selector24~0_I .shared_arith = "off";
defparam \Selector24~0_I .extended_lut = "off";
defparam \Selector24~0_I .lut_mask = "0000555500005555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector24~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[7] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[7]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[7] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[7]~reg0 ));
defparam \avs_cra_readdata[7]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[7]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[8]~4_I (
	.dataa(\__ALT_INV__avs_cra_address[3]~input0 ),
	.datab(\__ALT_INV__avs_cra_address[0]~input0 ),
	.datac(\__ALT_INV__avs_cra_address[2]~input0 ),
	.datad(\__ALT_INV__avs_cra_address[1]~input0 ),
	.datae(\__ALT_INV__avs_cra_write~input0 ),
	.dataf(\__ALT_INV__avs_cra_byteenable[1]~input0 ),
	.combout(\status_NO_SHIFT_REG[8]~4 ));
defparam \status_NO_SHIFT_REG[8]~4_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[8]~4_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[8]~4_I .lut_mask = "0000000000008000";

dffeas \status_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_writedata[8]~input0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\status_NO_SHIFT_REG[8]~4 ),
	.q(\status_NO_SHIFT_REG[8] ));
defparam \status_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector23~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[8] ),
	.combout(\Selector23~0 ));
defparam \Selector23~0_I .shared_arith = "off";
defparam \Selector23~0_I .extended_lut = "off";
defparam \Selector23~0_I .lut_mask = "0000000055555555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector23~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[8] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[8]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[8] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[8]~reg0 ));
defparam \avs_cra_readdata[8]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[8]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[9]~input0 ),
	.combout(\status_NO_SHIFT_REG[9]~feeder ));
defparam \status_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \status_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[9]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\status_NO_SHIFT_REG[8]~4 ),
	.q(\status_NO_SHIFT_REG[9] ));
defparam \status_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector22~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[9] ),
	.combout(\Selector22~0 ));
defparam \Selector22~0_I .shared_arith = "off";
defparam \Selector22~0_I .extended_lut = "off";
defparam \Selector22~0_I .lut_mask = "0000000055555555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector22~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[9] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[9]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[9] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[9]~reg0 ));
defparam \avs_cra_readdata[9]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[9]~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \status_NO_SHIFT_REG[10]~feeder_I (
	.dataf(\__ALT_INV__avs_cra_writedata[10]~input0 ),
	.combout(\status_NO_SHIFT_REG[10]~feeder ));
defparam \status_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \status_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \status_NO_SHIFT_REG[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \status_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\status_NO_SHIFT_REG[10]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\status_NO_SHIFT_REG[8]~4 ),
	.q(\status_NO_SHIFT_REG[10] ));
defparam \status_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector21~0_I (
	.datac(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[10] ),
	.combout(\Selector21~0 ));
defparam \Selector21~0_I .shared_arith = "off";
defparam \Selector21~0_I .extended_lut = "off";
defparam \Selector21~0_I .lut_mask = "000000000F0F0F0F";

dffeas \cra_readdata_st1_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector21~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[10] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[10]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[10] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[10]~reg0 ));
defparam \avs_cra_readdata[10]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[10]~reg0_I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|has_a_lsu_active~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|has_a_lsu_active~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|has_a_lsu_active ));
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|has_a_lsu_active~I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|has_a_lsu_active ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\status_NO_SHIFT_REG[13] ));
defparam \status_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector19~0_I (
	.dataa(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[13] ),
	.combout(\Selector19~0 ));
defparam \Selector19~0_I .shared_arith = "off";
defparam \Selector19~0_I .extended_lut = "off";
defparam \Selector19~0_I .lut_mask = "0000000055555555";

dffeas \cra_readdata_st1_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector19~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[12] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \avs_cra_readdata~0_I (
	.datab(\__ALT_INV__Equal0~0 ),
	.dataf(\__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[12] ),
	.combout(\avs_cra_readdata~0 ));
defparam \avs_cra_readdata~0_I .shared_arith = "off";
defparam \avs_cra_readdata~0_I .extended_lut = "off";
defparam \avs_cra_readdata~0_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \avs_cra_readdata[12]~reg0feeder_I (
	.dataf(\__ALT_INV__avs_cra_readdata~0 ),
	.combout(\avs_cra_readdata[12]~reg0feeder ));
defparam \avs_cra_readdata[12]~reg0feeder_I .shared_arith = "off";
defparam \avs_cra_readdata[12]~reg0feeder_I .extended_lut = "off";
defparam \avs_cra_readdata[12]~reg0feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \avs_cra_readdata[12]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.d(\avs_cra_readdata[12]~reg0feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\avs_cra_readdata[12]~reg0 ));
defparam \avs_cra_readdata[12]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[12]~reg0_I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[13]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.d(\avs_cra_readdata~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\avs_cra_readdata[13]~reg0 ));
defparam \avs_cra_readdata[13]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[13]~reg0_I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\acl_id_iterator:id_iter_inst0|acl_fifo:group_id_fifo|scfifo:scfifo_component|scfifo_25d1:auto_generated|a_dpfifo_s7a1:dpfifo|empty_dff ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\status_NO_SHIFT_REG[14] ));
defparam \status_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector17~0_I (
	.datae(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[14] ),
	.combout(\Selector17~0 ));
defparam \Selector17~0_I .shared_arith = "off";
defparam \Selector17~0_I .extended_lut = "off";
defparam \Selector17~0_I .lut_mask = "000000000000FFFF";

dffeas \cra_readdata_st1_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector17~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[14] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[14]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\cra_readdata_st1_NO_SHIFT_REG[14] ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[14]~reg0 ));
defparam \avs_cra_readdata[14]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[14]~reg0_I .is_wysiwyg = "true";

dffeas \status_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(started_NO_SHIFT_REG),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\status_NO_SHIFT_REG[15] ));
defparam \status_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \status_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \Selector16~0_I (
	.datae(\__ALT_INV__WideOr1~0 ),
	.dataf(\__ALT_INV__status_NO_SHIFT_REG[15] ),
	.combout(\Selector16~0 ));
defparam \Selector16~0_I .shared_arith = "off";
defparam \Selector16~0_I .extended_lut = "off";
defparam \Selector16~0_I .lut_mask = "000000000000FFFF";

dffeas \cra_readdata_st1_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\Selector16~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\cra_readdata_st1_NO_SHIFT_REG[15] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \avs_cra_readdata[15]~reg0feeder_I (
	.dataf(\__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[15] ),
	.combout(\avs_cra_readdata[15]~reg0feeder ));
defparam \avs_cra_readdata[15]~reg0feeder_I .shared_arith = "off";
defparam \avs_cra_readdata[15]~reg0feeder_I .extended_lut = "off";
defparam \avs_cra_readdata[15]~reg0feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \avs_cra_readdata[15]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.d(\avs_cra_readdata[15]~reg0feeder ),
	.clrn(\resetn~CLKENA0 ),
	.sclr(\Equal0~0 ),
	.q(\avs_cra_readdata[15]~reg0 ));
defparam \avs_cra_readdata[15]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[15]~reg0_I .is_wysiwyg = "true";

dffeas \cra_readdata_st1_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\WideOr1~0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\cra_readdata_st1_NO_SHIFT_REG[16] ));
defparam \cra_readdata_st1_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \cra_readdata_st1_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \avs_cra_readdata~1_I (
	.datac(\__ALT_INV__Equal0~0 ),
	.dataf(\__ALT_INV__cra_readdata_st1_NO_SHIFT_REG[16] ),
	.combout(\avs_cra_readdata~1 ));
defparam \avs_cra_readdata~1_I .shared_arith = "off";
defparam \avs_cra_readdata~1_I .extended_lut = "off";
defparam \avs_cra_readdata~1_I .lut_mask = "00000000F0F0F0F0";

dffeas \avs_cra_readdata[16]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\avs_cra_readdata~1 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\avs_cra_readdata[16]~reg0 ));
defparam \avs_cra_readdata[16]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[16]~reg0_I .is_wysiwyg = "true";

dffeas \avs_cra_readdata[17]~reg0_I (
	.clk(\clock~CLKENA0 ),
	.d(\avs_cra_readdata~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\avs_cra_readdata[17]~reg0 ));
defparam \avs_cra_readdata[17]~reg0_I .power_up = "low";
defparam \avs_cra_readdata[17]~reg0_I .is_wysiwyg = "true";

assign \avs_cra_read~input0  = avs_cra_read;

cyclonev_lcell_comb \cra_read_st1_NO_SHIFT_REG~feeder_I (
	.dataf(\__ALT_INV__avs_cra_read~input0 ),
	.combout(\cra_read_st1_NO_SHIFT_REG~feeder ));
defparam \cra_read_st1_NO_SHIFT_REG~feeder_I .shared_arith = "off";
defparam \cra_read_st1_NO_SHIFT_REG~feeder_I .extended_lut = "off";
defparam \cra_read_st1_NO_SHIFT_REG~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \cra_read_st1_NO_SHIFT_REG~I (
	.clk(\clock~CLKENA0 ),
	.d(\cra_read_st1_NO_SHIFT_REG~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(cra_read_st1_NO_SHIFT_REG));
defparam \cra_read_st1_NO_SHIFT_REG~I .power_up = "low";
defparam \cra_read_st1_NO_SHIFT_REG~I .is_wysiwyg = "true";

cyclonev_lcell_comb \avs_cra_readdatavalid~reg0feeder_I (
	.datab(__ALT_INV__cra_read_st1_NO_SHIFT_REG),
	.combout(\avs_cra_readdatavalid~reg0feeder ));
defparam \avs_cra_readdatavalid~reg0feeder_I .shared_arith = "off";
defparam \avs_cra_readdatavalid~reg0feeder_I .extended_lut = "off";
defparam \avs_cra_readdatavalid~reg0feeder_I .lut_mask = "3333333333333333";

dffeas \avs_cra_readdatavalid~reg0_I (
	.clk(\clock~CLKENA0 ),
	.d(\avs_cra_readdatavalid~reg0feeder ),
	.clrn(\resetn~CLKENA0 ),
	.q(\avs_cra_readdatavalid~reg0 ));
defparam \avs_cra_readdatavalid~reg0_I .power_up = "low";
defparam \avs_cra_readdatavalid~reg0_I .is_wysiwyg = "true";

cyclonev_lcell_comb \cra_irq~0_I (
	.datac(\__ALT_INV__status_NO_SHIFT_REG[1] ),
	.datae(\__ALT_INV__status_NO_SHIFT_REG[3] ),
	.combout(\cra_irq~0 ));
defparam \cra_irq~0_I .shared_arith = "off";
defparam \cra_irq~0_I .extended_lut = "off";
defparam \cra_irq~0_I .lut_mask = "0F0FFFFF0F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FFFF0000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .lut_mask = "32FF32FF00CD00CD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.dataf(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .lut_mask = "3030303020202020";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00CD00CD32FF32FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .lut_mask = "03CF03CF02DF02DF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00CD00CD32FF32FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .lut_mask = "03CF03CF02DF02DF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~4 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE_I .created_from = "Q(num_burst[2])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2]~DUPLICATE ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|always0~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE_I .created_from = "Q(num_burst[3])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3]~DUPLICATE ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .lut_mask = "0FFF00FA0FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0_I .lut_mask = "30FC30FC20FD20FD";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3_I .lut_mask = "0000FAFA00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|_~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I (
	.dataa(\__ALT_INV__avm_local_bb1_ld__u0_inst0_waitrequest~input0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__avm_read ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7_I .lut_mask = "00CD00CD32FF32FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[1]~DUPLICATE ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|num_burst[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__init ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|__ALT_INV__R_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__valid_burst~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__reset_cnt~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0_I .lut_mask = "0FAE0FFF0FAE0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[5] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[9] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[10] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[11] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[12] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[13] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[14] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[15] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[16] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[17] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[18] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[20] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[21] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[22] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|o_data[29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[24] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_io_pipeline:GEN_PIPE_INPUT.in_pipeline|__ALT_INV__o_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|addr_hold[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|__ALT_INV__addr_hold[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_num_burst[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[10] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[11] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[12] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[13] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[14] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[15] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[16] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[17] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[18] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[19] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[20] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[21] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[22] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[23] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[24] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr_valid ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|valid_rreq~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|acl_stall_free_coalescer:coalescer|o_page_addr[25] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_request_fifo|scfifo_u3g1:auto_generated|a_dpfifo_6ca1:dpfifo|altsyncram_fkn1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[5] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[5]~0_I .lut_mask = "0000AAAA5555FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[6]~1_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[7] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[7]~2_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[8] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[8]~3_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[9]~4_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[10] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[10]~5_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[11]~6_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[12] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[12]~7_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[13]~8_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[14] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[14]~9_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[15] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[15]~10_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[16]~11_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[17]~12_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[18]~13_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[19]~14_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[20]~15_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[21]~16_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[22] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[22]~17_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[23]~18_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[24]~19_I .lut_mask = "00FF00FF33333333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[25]~20_I .lut_mask = "0000AAAA5555FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[26] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[26]~21_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[27] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[27] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[27]~22_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|q_b[28] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][28] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[28]~23_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][29] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[29]~24_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_u4d1:auto_generated|a_dpfifo_o7a1:dpfifo|altsyncram_pgn1:FIFOram|__ALT_INV__q_b[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][30] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo2|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[30]~25_I .lut_mask = "0000F0F00F0FFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~1_I .lut_mask = "03030303030F030F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~0_I .lut_mask = "CCCCCCCCFF00FF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2_I .lut_mask = "0F0F0F0F0FFF0FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|__ALT_INV__q_b[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~feeder ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE_I .created_from = "Q(data[0][3])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][3]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27_I .lut_mask = "0000AAAA5555FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[3]~27 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[2] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[2]~26 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE_I .created_from = "Q(wrreq_delaya[1])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[1]~DUPLICATE ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|wrreq_delaya[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__empty_dff ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_1_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__usedw_is_2_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__wrreq_delaya[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0_I .lut_mask = "4577407F0033003F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2]~I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[2]~I .lut_mask = "0000000000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .lut_mask = "0000FFFF00000000";

assign \avm_local_bb1_ld__u0_inst0_readdata[14]~input0  = avm_local_bb1_ld__u0_inst0_readdata[14];

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~DUPLICATE_I .created_from = "Q(rd_ptr_lsb)";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .lut_mask = "0AFF0AFF00F500F5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .lut_mask = "0100010000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .lut_mask = "05AF05AF00FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .lut_mask = "05AF05AF00FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .lut_mask = "05AF05AF00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .lut_mask = "00AF00AF50FF50FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .lut_mask = "04BF04BF04BF04BF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .lut_mask = "00BB00BB44FF44FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .lut_mask = "00BB00BB44FF44FF";

assign \avm_local_bb1_ld__u0_inst0_readdata[15]~input0  = avm_local_bb1_ld__u0_inst0_readdata[15];

assign \avm_local_bb1_ld__u0_inst0_readdata[29]~input0  = avm_local_bb1_ld__u0_inst0_readdata[29];

assign \avm_local_bb1_ld__u0_inst0_readdata[30]~input0  = avm_local_bb1_ld__u0_inst0_readdata[30];

assign \avm_local_bb1_ld__u0_inst0_readdata[31]~input0  = avm_local_bb1_ld__u0_inst0_readdata[31];

assign \avm_local_bb1_ld__u0_inst0_readdata[46]~input0  = avm_local_bb1_ld__u0_inst0_readdata[46];

assign \avm_local_bb1_ld__u0_inst0_readdata[47]~input0  = avm_local_bb1_ld__u0_inst0_readdata[47];

assign \avm_local_bb1_ld__u0_inst0_readdata[61]~input0  = avm_local_bb1_ld__u0_inst0_readdata[61];

assign \avm_local_bb1_ld__u0_inst0_readdata[62]~input0  = avm_local_bb1_ld__u0_inst0_readdata[62];

assign \avm_local_bb1_ld__u0_inst0_readdata[63]~input0  = avm_local_bb1_ld__u0_inst0_readdata[63];

assign \avm_local_bb1_ld__u0_inst0_readdata[78]~input0  = avm_local_bb1_ld__u0_inst0_readdata[78];

assign \avm_local_bb1_ld__u0_inst0_readdata[79]~input0  = avm_local_bb1_ld__u0_inst0_readdata[79];

assign \avm_local_bb1_ld__u0_inst0_readdata[93]~input0  = avm_local_bb1_ld__u0_inst0_readdata[93];

assign \avm_local_bb1_ld__u0_inst0_readdata[94]~input0  = avm_local_bb1_ld__u0_inst0_readdata[94];

assign \avm_local_bb1_ld__u0_inst0_readdata[95]~input0  = avm_local_bb1_ld__u0_inst0_readdata[95];

assign \avm_local_bb1_ld__u0_inst0_readdata[110]~input0  = avm_local_bb1_ld__u0_inst0_readdata[110];

assign \avm_local_bb1_ld__u0_inst0_readdata[111]~input0  = avm_local_bb1_ld__u0_inst0_readdata[111];

assign \avm_local_bb1_ld__u0_inst0_readdata[125]~input0  = avm_local_bb1_ld__u0_inst0_readdata[125];

assign \avm_local_bb1_ld__u0_inst0_readdata[126]~input0  = avm_local_bb1_ld__u0_inst0_readdata[126];

assign \avm_local_bb1_ld__u0_inst0_readdata[127]~input0  = avm_local_bb1_ld__u0_inst0_readdata[127];

assign \avm_local_bb1_ld__u0_inst0_readdata[142]~input0  = avm_local_bb1_ld__u0_inst0_readdata[142];

assign \avm_local_bb1_ld__u0_inst0_readdata[143]~input0  = avm_local_bb1_ld__u0_inst0_readdata[143];

assign \avm_local_bb1_ld__u0_inst0_readdata[157]~input0  = avm_local_bb1_ld__u0_inst0_readdata[157];

assign \avm_local_bb1_ld__u0_inst0_readdata[158]~input0  = avm_local_bb1_ld__u0_inst0_readdata[158];

assign \avm_local_bb1_ld__u0_inst0_readdata[159]~input0  = avm_local_bb1_ld__u0_inst0_readdata[159];

assign \avm_local_bb1_ld__u0_inst0_readdata[174]~input0  = avm_local_bb1_ld__u0_inst0_readdata[174];

assign \avm_local_bb1_ld__u0_inst0_readdata[175]~input0  = avm_local_bb1_ld__u0_inst0_readdata[175];

assign \avm_local_bb1_ld__u0_inst0_readdata[189]~input0  = avm_local_bb1_ld__u0_inst0_readdata[189];

assign \avm_local_bb1_ld__u0_inst0_readdata[190]~input0  = avm_local_bb1_ld__u0_inst0_readdata[190];

assign \avm_local_bb1_ld__u0_inst0_readdata[191]~input0  = avm_local_bb1_ld__u0_inst0_readdata[191];

assign \avm_local_bb1_ld__u0_inst0_readdata[206]~input0  = avm_local_bb1_ld__u0_inst0_readdata[206];

assign \avm_local_bb1_ld__u0_inst0_readdata[207]~input0  = avm_local_bb1_ld__u0_inst0_readdata[207];

assign \avm_local_bb1_ld__u0_inst0_readdata[221]~input0  = avm_local_bb1_ld__u0_inst0_readdata[221];

assign \avm_local_bb1_ld__u0_inst0_readdata[222]~input0  = avm_local_bb1_ld__u0_inst0_readdata[222];

assign \avm_local_bb1_ld__u0_inst0_readdata[223]~input0  = avm_local_bb1_ld__u0_inst0_readdata[223];

assign \avm_local_bb1_ld__u0_inst0_readdata[238]~input0  = avm_local_bb1_ld__u0_inst0_readdata[238];

assign \avm_local_bb1_ld__u0_inst0_readdata[239]~input0  = avm_local_bb1_ld__u0_inst0_readdata[239];

assign \avm_local_bb1_ld__u0_inst0_readdata[253]~input0  = avm_local_bb1_ld__u0_inst0_readdata[253];

assign \avm_local_bb1_ld__u0_inst0_readdata[254]~input0  = avm_local_bb1_ld__u0_inst0_readdata[254];

assign \avm_local_bb1_ld__u0_inst0_readdata[255]~input0  = avm_local_bb1_ld__u0_inst0_readdata[255];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[14]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[15]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[29]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[30]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[31]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_first_bit_number = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_first_bit_number = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[46]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[47]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[61]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[62]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[63]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[78]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[79]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[93]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[94]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[95]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[110]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[111]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[125]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[126]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[127]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[142]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[143]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[157]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[158]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[159]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[174]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[175]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[189]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[190]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[191]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[206]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_first_bit_number = 206;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_first_bit_number = 206;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[207]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_first_bit_number = 207;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_first_bit_number = 207;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[221]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_first_bit_number = 221;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_first_bit_number = 221;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[222]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_first_bit_number = 222;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_first_bit_number = 222;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[223]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_first_bit_number = 223;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_first_bit_number = 223;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[238]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_first_bit_number = 238;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_first_bit_number = 238;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[239]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_first_bit_number = 239;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_first_bit_number = 239;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[253]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_first_bit_number = 253;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_first_bit_number = 253;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[254]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_first_bit_number = 254;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_first_bit_number = 254;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[255]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_first_bit_number = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_first_bit_number = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~DUPLICATE_I .created_from = "Q(R_offset[0])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .created_from = "Q(R_offset[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .lut_mask = "04073437C4C7F4F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .lut_mask = "000F3355FF0F3355";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[29] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1_I .lut_mask = "5555000055550000";

assign \avm_local_bb1_ld__inst0_readdata[14]~input0  = avm_local_bb1_ld__inst0_readdata[14];

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|__ALT_INV__counter_reg_bit[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita6~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_comb_bita7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FF00FF00FF00FF00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0_I .lut_mask = "44FF44FF00BB00BB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__offset_valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__empty_dff ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5_I .lut_mask = "0004000400000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1_I .lut_mask = "05AF05AF00FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2_I .lut_mask = "0505F5F50000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3_I .lut_mask = "00BB00BB44FF44FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4_I .lut_mask = "00BB00BB44FF44FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5_I .lut_mask = "00BB00BB44FF44FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita4~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6_I .lut_mask = "0000AFAF5050FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|low_addressa[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita5~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_comb_bita6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|counter_reg_bit[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__valid_rreq~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__data_stall~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|__ALT_INV__low_addressa[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_kgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7_I .lut_mask = "00BB00BB44FF44FF";

assign \avm_local_bb1_ld__inst0_readdata[15]~input0  = avm_local_bb1_ld__inst0_readdata[15];

assign \avm_local_bb1_ld__inst0_readdata[29]~input0  = avm_local_bb1_ld__inst0_readdata[29];

assign \avm_local_bb1_ld__inst0_readdata[30]~input0  = avm_local_bb1_ld__inst0_readdata[30];

assign \avm_local_bb1_ld__inst0_readdata[31]~input0  = avm_local_bb1_ld__inst0_readdata[31];

assign \avm_local_bb1_ld__inst0_readdata[46]~input0  = avm_local_bb1_ld__inst0_readdata[46];

assign \avm_local_bb1_ld__inst0_readdata[47]~input0  = avm_local_bb1_ld__inst0_readdata[47];

assign \avm_local_bb1_ld__inst0_readdata[61]~input0  = avm_local_bb1_ld__inst0_readdata[61];

assign \avm_local_bb1_ld__inst0_readdata[62]~input0  = avm_local_bb1_ld__inst0_readdata[62];

assign \avm_local_bb1_ld__inst0_readdata[63]~input0  = avm_local_bb1_ld__inst0_readdata[63];

assign \avm_local_bb1_ld__inst0_readdata[78]~input0  = avm_local_bb1_ld__inst0_readdata[78];

assign \avm_local_bb1_ld__inst0_readdata[79]~input0  = avm_local_bb1_ld__inst0_readdata[79];

assign \avm_local_bb1_ld__inst0_readdata[93]~input0  = avm_local_bb1_ld__inst0_readdata[93];

assign \avm_local_bb1_ld__inst0_readdata[94]~input0  = avm_local_bb1_ld__inst0_readdata[94];

assign \avm_local_bb1_ld__inst0_readdata[95]~input0  = avm_local_bb1_ld__inst0_readdata[95];

assign \avm_local_bb1_ld__inst0_readdata[110]~input0  = avm_local_bb1_ld__inst0_readdata[110];

assign \avm_local_bb1_ld__inst0_readdata[111]~input0  = avm_local_bb1_ld__inst0_readdata[111];

assign \avm_local_bb1_ld__inst0_readdata[125]~input0  = avm_local_bb1_ld__inst0_readdata[125];

assign \avm_local_bb1_ld__inst0_readdata[126]~input0  = avm_local_bb1_ld__inst0_readdata[126];

assign \avm_local_bb1_ld__inst0_readdata[127]~input0  = avm_local_bb1_ld__inst0_readdata[127];

assign \avm_local_bb1_ld__inst0_readdata[142]~input0  = avm_local_bb1_ld__inst0_readdata[142];

assign \avm_local_bb1_ld__inst0_readdata[143]~input0  = avm_local_bb1_ld__inst0_readdata[143];

assign \avm_local_bb1_ld__inst0_readdata[157]~input0  = avm_local_bb1_ld__inst0_readdata[157];

assign \avm_local_bb1_ld__inst0_readdata[158]~input0  = avm_local_bb1_ld__inst0_readdata[158];

assign \avm_local_bb1_ld__inst0_readdata[159]~input0  = avm_local_bb1_ld__inst0_readdata[159];

assign \avm_local_bb1_ld__inst0_readdata[174]~input0  = avm_local_bb1_ld__inst0_readdata[174];

assign \avm_local_bb1_ld__inst0_readdata[175]~input0  = avm_local_bb1_ld__inst0_readdata[175];

assign \avm_local_bb1_ld__inst0_readdata[189]~input0  = avm_local_bb1_ld__inst0_readdata[189];

assign \avm_local_bb1_ld__inst0_readdata[190]~input0  = avm_local_bb1_ld__inst0_readdata[190];

assign \avm_local_bb1_ld__inst0_readdata[191]~input0  = avm_local_bb1_ld__inst0_readdata[191];

assign \avm_local_bb1_ld__inst0_readdata[206]~input0  = avm_local_bb1_ld__inst0_readdata[206];

assign \avm_local_bb1_ld__inst0_readdata[207]~input0  = avm_local_bb1_ld__inst0_readdata[207];

assign \avm_local_bb1_ld__inst0_readdata[221]~input0  = avm_local_bb1_ld__inst0_readdata[221];

assign \avm_local_bb1_ld__inst0_readdata[222]~input0  = avm_local_bb1_ld__inst0_readdata[222];

assign \avm_local_bb1_ld__inst0_readdata[223]~input0  = avm_local_bb1_ld__inst0_readdata[223];

assign \avm_local_bb1_ld__inst0_readdata[238]~input0  = avm_local_bb1_ld__inst0_readdata[238];

assign \avm_local_bb1_ld__inst0_readdata[239]~input0  = avm_local_bb1_ld__inst0_readdata[239];

assign \avm_local_bb1_ld__inst0_readdata[253]~input0  = avm_local_bb1_ld__inst0_readdata[253];

assign \avm_local_bb1_ld__inst0_readdata[254]~input0  = avm_local_bb1_ld__inst0_readdata[254];

assign \avm_local_bb1_ld__inst0_readdata[255]~input0  = avm_local_bb1_ld__inst0_readdata[255];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[14]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[14] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_first_bit_number = 14;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a14 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[15]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[15] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_first_bit_number = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a15 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[29]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[29] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_first_bit_number = 29;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a29 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[30]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[30] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_first_bit_number = 30;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a30 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[31]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[31] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_first_bit_number = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_first_bit_number = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a31 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[46]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[46] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a46 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[47]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[47] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a47 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[61]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[61] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a61 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[62]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[62] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a62 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[63]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[63] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a63 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[78]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[78] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a78 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[79]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[79] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a79 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[93]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[93] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a93 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[94]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[94] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a94 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[95]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[95] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a95 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[110]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[110] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a110 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[111]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[111] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a111 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[125]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[125] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a125 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[126]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[126] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a126 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[127]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[127] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a127 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[142]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[142] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a142 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[143]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[143] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a143 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[157]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[157] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a157 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[158]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[158] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a158 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[159]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[159] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a159 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[174]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[174] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a174 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[175]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[175] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a175 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[189]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[189] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a189 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[190]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[190] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a190 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[191]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[191] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a191 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[206]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[206] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_first_bit_number = 206;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_first_bit_number = 206;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a206 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[207]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[207] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_first_bit_number = 207;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_first_bit_number = 207;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a207 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[221]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[221] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_first_bit_number = 221;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_first_bit_number = 221;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a221 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[222]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[222] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_first_bit_number = 222;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_first_bit_number = 222;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a222 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[223]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[223] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_first_bit_number = 223;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_first_bit_number = 223;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a223 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[238]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[238] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_first_bit_number = 238;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_first_bit_number = 238;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a238 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[239]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[239] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_first_bit_number = 239;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_first_bit_number = 239;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a239 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[253]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[253] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_first_bit_number = 253;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_first_bit_number = 253;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a253 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[254]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[254] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_first_bit_number = 254;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_first_bit_number = 254;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a254 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[255]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[255] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_first_bit_number = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_first_bit_number = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a255 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~DUPLICATE_I .created_from = "Q(R_offset[1])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[29] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[61] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[125] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[93] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~7_I .lut_mask = "5533000F5533FF0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|__ALT_INV__q_b[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[157] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[221] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[189] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[253] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~6_I .lut_mask = "555533330F0F00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~7 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8_I .lut_mask = "4444777744447777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~8 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[29] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__u0_inst0_readdata[16]~input0  = avm_local_bb1_ld__u0_inst0_readdata[16];

assign \avm_local_bb1_ld__u0_inst0_readdata[18]~input0  = avm_local_bb1_ld__u0_inst0_readdata[18];

assign \avm_local_bb1_ld__u0_inst0_readdata[21]~input0  = avm_local_bb1_ld__u0_inst0_readdata[21];

assign \avm_local_bb1_ld__u0_inst0_readdata[22]~input0  = avm_local_bb1_ld__u0_inst0_readdata[22];

assign \avm_local_bb1_ld__u0_inst0_readdata[23]~input0  = avm_local_bb1_ld__u0_inst0_readdata[23];

assign \avm_local_bb1_ld__u0_inst0_readdata[48]~input0  = avm_local_bb1_ld__u0_inst0_readdata[48];

assign \avm_local_bb1_ld__u0_inst0_readdata[50]~input0  = avm_local_bb1_ld__u0_inst0_readdata[50];

assign \avm_local_bb1_ld__u0_inst0_readdata[53]~input0  = avm_local_bb1_ld__u0_inst0_readdata[53];

assign \avm_local_bb1_ld__u0_inst0_readdata[54]~input0  = avm_local_bb1_ld__u0_inst0_readdata[54];

assign \avm_local_bb1_ld__u0_inst0_readdata[55]~input0  = avm_local_bb1_ld__u0_inst0_readdata[55];

assign \avm_local_bb1_ld__u0_inst0_readdata[80]~input0  = avm_local_bb1_ld__u0_inst0_readdata[80];

assign \avm_local_bb1_ld__u0_inst0_readdata[82]~input0  = avm_local_bb1_ld__u0_inst0_readdata[82];

assign \avm_local_bb1_ld__u0_inst0_readdata[85]~input0  = avm_local_bb1_ld__u0_inst0_readdata[85];

assign \avm_local_bb1_ld__u0_inst0_readdata[86]~input0  = avm_local_bb1_ld__u0_inst0_readdata[86];

assign \avm_local_bb1_ld__u0_inst0_readdata[87]~input0  = avm_local_bb1_ld__u0_inst0_readdata[87];

assign \avm_local_bb1_ld__u0_inst0_readdata[112]~input0  = avm_local_bb1_ld__u0_inst0_readdata[112];

assign \avm_local_bb1_ld__u0_inst0_readdata[114]~input0  = avm_local_bb1_ld__u0_inst0_readdata[114];

assign \avm_local_bb1_ld__u0_inst0_readdata[117]~input0  = avm_local_bb1_ld__u0_inst0_readdata[117];

assign \avm_local_bb1_ld__u0_inst0_readdata[118]~input0  = avm_local_bb1_ld__u0_inst0_readdata[118];

assign \avm_local_bb1_ld__u0_inst0_readdata[119]~input0  = avm_local_bb1_ld__u0_inst0_readdata[119];

assign \avm_local_bb1_ld__u0_inst0_readdata[144]~input0  = avm_local_bb1_ld__u0_inst0_readdata[144];

assign \avm_local_bb1_ld__u0_inst0_readdata[146]~input0  = avm_local_bb1_ld__u0_inst0_readdata[146];

assign \avm_local_bb1_ld__u0_inst0_readdata[149]~input0  = avm_local_bb1_ld__u0_inst0_readdata[149];

assign \avm_local_bb1_ld__u0_inst0_readdata[150]~input0  = avm_local_bb1_ld__u0_inst0_readdata[150];

assign \avm_local_bb1_ld__u0_inst0_readdata[151]~input0  = avm_local_bb1_ld__u0_inst0_readdata[151];

assign \avm_local_bb1_ld__u0_inst0_readdata[176]~input0  = avm_local_bb1_ld__u0_inst0_readdata[176];

assign \avm_local_bb1_ld__u0_inst0_readdata[178]~input0  = avm_local_bb1_ld__u0_inst0_readdata[178];

assign \avm_local_bb1_ld__u0_inst0_readdata[181]~input0  = avm_local_bb1_ld__u0_inst0_readdata[181];

assign \avm_local_bb1_ld__u0_inst0_readdata[182]~input0  = avm_local_bb1_ld__u0_inst0_readdata[182];

assign \avm_local_bb1_ld__u0_inst0_readdata[183]~input0  = avm_local_bb1_ld__u0_inst0_readdata[183];

assign \avm_local_bb1_ld__u0_inst0_readdata[208]~input0  = avm_local_bb1_ld__u0_inst0_readdata[208];

assign \avm_local_bb1_ld__u0_inst0_readdata[210]~input0  = avm_local_bb1_ld__u0_inst0_readdata[210];

assign \avm_local_bb1_ld__u0_inst0_readdata[213]~input0  = avm_local_bb1_ld__u0_inst0_readdata[213];

assign \avm_local_bb1_ld__u0_inst0_readdata[214]~input0  = avm_local_bb1_ld__u0_inst0_readdata[214];

assign \avm_local_bb1_ld__u0_inst0_readdata[215]~input0  = avm_local_bb1_ld__u0_inst0_readdata[215];

assign \avm_local_bb1_ld__u0_inst0_readdata[240]~input0  = avm_local_bb1_ld__u0_inst0_readdata[240];

assign \avm_local_bb1_ld__u0_inst0_readdata[242]~input0  = avm_local_bb1_ld__u0_inst0_readdata[242];

assign \avm_local_bb1_ld__u0_inst0_readdata[245]~input0  = avm_local_bb1_ld__u0_inst0_readdata[245];

assign \avm_local_bb1_ld__u0_inst0_readdata[246]~input0  = avm_local_bb1_ld__u0_inst0_readdata[246];

assign \avm_local_bb1_ld__u0_inst0_readdata[247]~input0  = avm_local_bb1_ld__u0_inst0_readdata[247];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[16]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[18]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[21]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[22]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[23]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[48]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[50]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[53]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[54]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[55]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[80]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[82]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[85]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[86]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[87]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[112]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[114]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[117]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[118]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[119]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[144]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[146]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[149]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[150]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[151]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[176]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[178]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[181]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[182]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[183]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[208]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_first_bit_number = 208;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_first_bit_number = 208;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[210]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_first_bit_number = 210;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_first_bit_number = 210;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[213]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_first_bit_number = 213;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_first_bit_number = 213;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[214]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_first_bit_number = 214;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_first_bit_number = 214;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[215]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_first_bit_number = 215;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_first_bit_number = 215;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[240]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_first_bit_number = 240;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_first_bit_number = 240;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[242]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_first_bit_number = 242;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_first_bit_number = 242;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[245]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_first_bit_number = 245;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_first_bit_number = 245;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[246]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_first_bit_number = 246;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_first_bit_number = 246;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[247]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_first_bit_number = 247;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_first_bit_number = 247;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .lut_mask = "04268CAE15379DBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .lut_mask = "0C3F44440C3F7777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[23] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__inst0_readdata[16]~input0  = avm_local_bb1_ld__inst0_readdata[16];

assign \avm_local_bb1_ld__inst0_readdata[18]~input0  = avm_local_bb1_ld__inst0_readdata[18];

assign \avm_local_bb1_ld__inst0_readdata[21]~input0  = avm_local_bb1_ld__inst0_readdata[21];

assign \avm_local_bb1_ld__inst0_readdata[22]~input0  = avm_local_bb1_ld__inst0_readdata[22];

assign \avm_local_bb1_ld__inst0_readdata[23]~input0  = avm_local_bb1_ld__inst0_readdata[23];

assign \avm_local_bb1_ld__inst0_readdata[48]~input0  = avm_local_bb1_ld__inst0_readdata[48];

assign \avm_local_bb1_ld__inst0_readdata[50]~input0  = avm_local_bb1_ld__inst0_readdata[50];

assign \avm_local_bb1_ld__inst0_readdata[53]~input0  = avm_local_bb1_ld__inst0_readdata[53];

assign \avm_local_bb1_ld__inst0_readdata[54]~input0  = avm_local_bb1_ld__inst0_readdata[54];

assign \avm_local_bb1_ld__inst0_readdata[55]~input0  = avm_local_bb1_ld__inst0_readdata[55];

assign \avm_local_bb1_ld__inst0_readdata[80]~input0  = avm_local_bb1_ld__inst0_readdata[80];

assign \avm_local_bb1_ld__inst0_readdata[82]~input0  = avm_local_bb1_ld__inst0_readdata[82];

assign \avm_local_bb1_ld__inst0_readdata[85]~input0  = avm_local_bb1_ld__inst0_readdata[85];

assign \avm_local_bb1_ld__inst0_readdata[86]~input0  = avm_local_bb1_ld__inst0_readdata[86];

assign \avm_local_bb1_ld__inst0_readdata[87]~input0  = avm_local_bb1_ld__inst0_readdata[87];

assign \avm_local_bb1_ld__inst0_readdata[112]~input0  = avm_local_bb1_ld__inst0_readdata[112];

assign \avm_local_bb1_ld__inst0_readdata[114]~input0  = avm_local_bb1_ld__inst0_readdata[114];

assign \avm_local_bb1_ld__inst0_readdata[117]~input0  = avm_local_bb1_ld__inst0_readdata[117];

assign \avm_local_bb1_ld__inst0_readdata[118]~input0  = avm_local_bb1_ld__inst0_readdata[118];

assign \avm_local_bb1_ld__inst0_readdata[119]~input0  = avm_local_bb1_ld__inst0_readdata[119];

assign \avm_local_bb1_ld__inst0_readdata[144]~input0  = avm_local_bb1_ld__inst0_readdata[144];

assign \avm_local_bb1_ld__inst0_readdata[146]~input0  = avm_local_bb1_ld__inst0_readdata[146];

assign \avm_local_bb1_ld__inst0_readdata[149]~input0  = avm_local_bb1_ld__inst0_readdata[149];

assign \avm_local_bb1_ld__inst0_readdata[150]~input0  = avm_local_bb1_ld__inst0_readdata[150];

assign \avm_local_bb1_ld__inst0_readdata[151]~input0  = avm_local_bb1_ld__inst0_readdata[151];

assign \avm_local_bb1_ld__inst0_readdata[176]~input0  = avm_local_bb1_ld__inst0_readdata[176];

assign \avm_local_bb1_ld__inst0_readdata[178]~input0  = avm_local_bb1_ld__inst0_readdata[178];

assign \avm_local_bb1_ld__inst0_readdata[181]~input0  = avm_local_bb1_ld__inst0_readdata[181];

assign \avm_local_bb1_ld__inst0_readdata[182]~input0  = avm_local_bb1_ld__inst0_readdata[182];

assign \avm_local_bb1_ld__inst0_readdata[183]~input0  = avm_local_bb1_ld__inst0_readdata[183];

assign \avm_local_bb1_ld__inst0_readdata[208]~input0  = avm_local_bb1_ld__inst0_readdata[208];

assign \avm_local_bb1_ld__inst0_readdata[210]~input0  = avm_local_bb1_ld__inst0_readdata[210];

assign \avm_local_bb1_ld__inst0_readdata[213]~input0  = avm_local_bb1_ld__inst0_readdata[213];

assign \avm_local_bb1_ld__inst0_readdata[214]~input0  = avm_local_bb1_ld__inst0_readdata[214];

assign \avm_local_bb1_ld__inst0_readdata[215]~input0  = avm_local_bb1_ld__inst0_readdata[215];

assign \avm_local_bb1_ld__inst0_readdata[240]~input0  = avm_local_bb1_ld__inst0_readdata[240];

assign \avm_local_bb1_ld__inst0_readdata[242]~input0  = avm_local_bb1_ld__inst0_readdata[242];

assign \avm_local_bb1_ld__inst0_readdata[245]~input0  = avm_local_bb1_ld__inst0_readdata[245];

assign \avm_local_bb1_ld__inst0_readdata[246]~input0  = avm_local_bb1_ld__inst0_readdata[246];

assign \avm_local_bb1_ld__inst0_readdata[247]~input0  = avm_local_bb1_ld__inst0_readdata[247];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[16]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[16] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_first_bit_number = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a16 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[18]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[18] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_first_bit_number = 18;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a18 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[21]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[21] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_first_bit_number = 21;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a21 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[22]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[22] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_first_bit_number = 22;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a22 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[23]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[23] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_first_bit_number = 23;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a23 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[48]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[48] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a48 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[50]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[50] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a50 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[53]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[53] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a53 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[54]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[54] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a54 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[55]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[55] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a55 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[80]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[80] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a80 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[82]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[82] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a82 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[85]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[85] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a85 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[86]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[86] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a86 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[87]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[87] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a87 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[112]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[112] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a112 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[114]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[114] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a114 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[117]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[117] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a117 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[118]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[118] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a118 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[119]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[119] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a119 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[144]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[144] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a144 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[146]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[146] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a146 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[149]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[149] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a149 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[150]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[150] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a150 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[151]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[151] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a151 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[176]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[176] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a176 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[178]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[178] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a178 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[181]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[181] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a181 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[182]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[182] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a182 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[183]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[183] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a183 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[208]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[208] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_first_bit_number = 208;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_first_bit_number = 208;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a208 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[210]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[210] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_first_bit_number = 210;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_first_bit_number = 210;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a210 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[213]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[213] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_first_bit_number = 213;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_first_bit_number = 213;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a213 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[214]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[214] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_first_bit_number = 214;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_first_bit_number = 214;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a214 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[215]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[215] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_first_bit_number = 215;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_first_bit_number = 215;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a215 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[240]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[240] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_first_bit_number = 240;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_first_bit_number = 240;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a240 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[242]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[242] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_first_bit_number = 242;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_first_bit_number = 242;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a242 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[245]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[245] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_first_bit_number = 245;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_first_bit_number = 245;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a245 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[246]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[246] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_first_bit_number = 246;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_first_bit_number = 246;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a246 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[247]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[247] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_first_bit_number = 247;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_first_bit_number = 247;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a247 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[215] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[183] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[151] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[247] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~63_I .lut_mask = "03CF03CF44447777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[55] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[23] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[87] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[119] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~64_I .lut_mask = "10D01CDC13D31FDF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~63 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~64 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65_I .lut_mask = "00330033CCFFCCFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~65 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[23] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .lut_mask = "550F3300550F33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .lut_mask = "05052277AFAF2277";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[22] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[182] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[214] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[150] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[246] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~60_I .lut_mask = "0252A2F20757A7F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[86] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[54] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[118] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~61_I .lut_mask = "535300F053530FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~60 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~61 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~62 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[22] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~0_I .lut_mask = "A500A50000A500A5";

assign \avm_local_bb1_ld__inst0_readdata[10]~input0  = avm_local_bb1_ld__inst0_readdata[10];

assign \avm_local_bb1_ld__inst0_readdata[11]~input0  = avm_local_bb1_ld__inst0_readdata[11];

assign \avm_local_bb1_ld__inst0_readdata[12]~input0  = avm_local_bb1_ld__inst0_readdata[12];

assign \avm_local_bb1_ld__inst0_readdata[13]~input0  = avm_local_bb1_ld__inst0_readdata[13];

assign \avm_local_bb1_ld__inst0_readdata[24]~input0  = avm_local_bb1_ld__inst0_readdata[24];

assign \avm_local_bb1_ld__inst0_readdata[42]~input0  = avm_local_bb1_ld__inst0_readdata[42];

assign \avm_local_bb1_ld__inst0_readdata[43]~input0  = avm_local_bb1_ld__inst0_readdata[43];

assign \avm_local_bb1_ld__inst0_readdata[44]~input0  = avm_local_bb1_ld__inst0_readdata[44];

assign \avm_local_bb1_ld__inst0_readdata[45]~input0  = avm_local_bb1_ld__inst0_readdata[45];

assign \avm_local_bb1_ld__inst0_readdata[56]~input0  = avm_local_bb1_ld__inst0_readdata[56];

assign \avm_local_bb1_ld__inst0_readdata[74]~input0  = avm_local_bb1_ld__inst0_readdata[74];

assign \avm_local_bb1_ld__inst0_readdata[75]~input0  = avm_local_bb1_ld__inst0_readdata[75];

assign \avm_local_bb1_ld__inst0_readdata[76]~input0  = avm_local_bb1_ld__inst0_readdata[76];

assign \avm_local_bb1_ld__inst0_readdata[77]~input0  = avm_local_bb1_ld__inst0_readdata[77];

assign \avm_local_bb1_ld__inst0_readdata[88]~input0  = avm_local_bb1_ld__inst0_readdata[88];

assign \avm_local_bb1_ld__inst0_readdata[106]~input0  = avm_local_bb1_ld__inst0_readdata[106];

assign \avm_local_bb1_ld__inst0_readdata[107]~input0  = avm_local_bb1_ld__inst0_readdata[107];

assign \avm_local_bb1_ld__inst0_readdata[108]~input0  = avm_local_bb1_ld__inst0_readdata[108];

assign \avm_local_bb1_ld__inst0_readdata[109]~input0  = avm_local_bb1_ld__inst0_readdata[109];

assign \avm_local_bb1_ld__inst0_readdata[120]~input0  = avm_local_bb1_ld__inst0_readdata[120];

assign \avm_local_bb1_ld__inst0_readdata[138]~input0  = avm_local_bb1_ld__inst0_readdata[138];

assign \avm_local_bb1_ld__inst0_readdata[139]~input0  = avm_local_bb1_ld__inst0_readdata[139];

assign \avm_local_bb1_ld__inst0_readdata[140]~input0  = avm_local_bb1_ld__inst0_readdata[140];

assign \avm_local_bb1_ld__inst0_readdata[141]~input0  = avm_local_bb1_ld__inst0_readdata[141];

assign \avm_local_bb1_ld__inst0_readdata[152]~input0  = avm_local_bb1_ld__inst0_readdata[152];

assign \avm_local_bb1_ld__inst0_readdata[170]~input0  = avm_local_bb1_ld__inst0_readdata[170];

assign \avm_local_bb1_ld__inst0_readdata[171]~input0  = avm_local_bb1_ld__inst0_readdata[171];

assign \avm_local_bb1_ld__inst0_readdata[172]~input0  = avm_local_bb1_ld__inst0_readdata[172];

assign \avm_local_bb1_ld__inst0_readdata[173]~input0  = avm_local_bb1_ld__inst0_readdata[173];

assign \avm_local_bb1_ld__inst0_readdata[184]~input0  = avm_local_bb1_ld__inst0_readdata[184];

assign \avm_local_bb1_ld__inst0_readdata[202]~input0  = avm_local_bb1_ld__inst0_readdata[202];

assign \avm_local_bb1_ld__inst0_readdata[203]~input0  = avm_local_bb1_ld__inst0_readdata[203];

assign \avm_local_bb1_ld__inst0_readdata[204]~input0  = avm_local_bb1_ld__inst0_readdata[204];

assign \avm_local_bb1_ld__inst0_readdata[205]~input0  = avm_local_bb1_ld__inst0_readdata[205];

assign \avm_local_bb1_ld__inst0_readdata[216]~input0  = avm_local_bb1_ld__inst0_readdata[216];

assign \avm_local_bb1_ld__inst0_readdata[234]~input0  = avm_local_bb1_ld__inst0_readdata[234];

assign \avm_local_bb1_ld__inst0_readdata[235]~input0  = avm_local_bb1_ld__inst0_readdata[235];

assign \avm_local_bb1_ld__inst0_readdata[236]~input0  = avm_local_bb1_ld__inst0_readdata[236];

assign \avm_local_bb1_ld__inst0_readdata[237]~input0  = avm_local_bb1_ld__inst0_readdata[237];

assign \avm_local_bb1_ld__inst0_readdata[248]~input0  = avm_local_bb1_ld__inst0_readdata[248];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[10]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[11]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[12]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[13]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[24]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[42]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[43]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[44]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[45]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[56]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[74]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[75]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[76]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[77]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[88]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[106]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[107]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[108]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[109]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[120]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[138]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[139]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[140]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[141]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[152]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[170]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[171]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[172]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[173]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[184]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[202]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[203]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[204]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_first_bit_number = 204;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_first_bit_number = 204;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[205]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_first_bit_number = 205;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_first_bit_number = 205;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[216]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_first_bit_number = 216;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_first_bit_number = 216;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[234]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_first_bit_number = 234;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_first_bit_number = 234;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[235]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_first_bit_number = 235;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_first_bit_number = 235;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[236]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_first_bit_number = 236;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_first_bit_number = 236;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[237]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_first_bit_number = 237;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_first_bit_number = 237;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[248]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_first_bit_number = 248;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_first_bit_number = 248;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .lut_mask = "084C195D2A6E3B7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .lut_mask = "470047CC473347FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE_I .created_from = "Q(local_bb1_ld__NO_SHIFT_REG[24])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[24]~DUPLICATE ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__u0_inst0_readdata[10]~input0  = avm_local_bb1_ld__u0_inst0_readdata[10];

assign \avm_local_bb1_ld__u0_inst0_readdata[11]~input0  = avm_local_bb1_ld__u0_inst0_readdata[11];

assign \avm_local_bb1_ld__u0_inst0_readdata[12]~input0  = avm_local_bb1_ld__u0_inst0_readdata[12];

assign \avm_local_bb1_ld__u0_inst0_readdata[13]~input0  = avm_local_bb1_ld__u0_inst0_readdata[13];

assign \avm_local_bb1_ld__u0_inst0_readdata[24]~input0  = avm_local_bb1_ld__u0_inst0_readdata[24];

assign \avm_local_bb1_ld__u0_inst0_readdata[42]~input0  = avm_local_bb1_ld__u0_inst0_readdata[42];

assign \avm_local_bb1_ld__u0_inst0_readdata[43]~input0  = avm_local_bb1_ld__u0_inst0_readdata[43];

assign \avm_local_bb1_ld__u0_inst0_readdata[44]~input0  = avm_local_bb1_ld__u0_inst0_readdata[44];

assign \avm_local_bb1_ld__u0_inst0_readdata[45]~input0  = avm_local_bb1_ld__u0_inst0_readdata[45];

assign \avm_local_bb1_ld__u0_inst0_readdata[56]~input0  = avm_local_bb1_ld__u0_inst0_readdata[56];

assign \avm_local_bb1_ld__u0_inst0_readdata[74]~input0  = avm_local_bb1_ld__u0_inst0_readdata[74];

assign \avm_local_bb1_ld__u0_inst0_readdata[75]~input0  = avm_local_bb1_ld__u0_inst0_readdata[75];

assign \avm_local_bb1_ld__u0_inst0_readdata[76]~input0  = avm_local_bb1_ld__u0_inst0_readdata[76];

assign \avm_local_bb1_ld__u0_inst0_readdata[77]~input0  = avm_local_bb1_ld__u0_inst0_readdata[77];

assign \avm_local_bb1_ld__u0_inst0_readdata[88]~input0  = avm_local_bb1_ld__u0_inst0_readdata[88];

assign \avm_local_bb1_ld__u0_inst0_readdata[106]~input0  = avm_local_bb1_ld__u0_inst0_readdata[106];

assign \avm_local_bb1_ld__u0_inst0_readdata[107]~input0  = avm_local_bb1_ld__u0_inst0_readdata[107];

assign \avm_local_bb1_ld__u0_inst0_readdata[108]~input0  = avm_local_bb1_ld__u0_inst0_readdata[108];

assign \avm_local_bb1_ld__u0_inst0_readdata[109]~input0  = avm_local_bb1_ld__u0_inst0_readdata[109];

assign \avm_local_bb1_ld__u0_inst0_readdata[120]~input0  = avm_local_bb1_ld__u0_inst0_readdata[120];

assign \avm_local_bb1_ld__u0_inst0_readdata[138]~input0  = avm_local_bb1_ld__u0_inst0_readdata[138];

assign \avm_local_bb1_ld__u0_inst0_readdata[139]~input0  = avm_local_bb1_ld__u0_inst0_readdata[139];

assign \avm_local_bb1_ld__u0_inst0_readdata[140]~input0  = avm_local_bb1_ld__u0_inst0_readdata[140];

assign \avm_local_bb1_ld__u0_inst0_readdata[141]~input0  = avm_local_bb1_ld__u0_inst0_readdata[141];

assign \avm_local_bb1_ld__u0_inst0_readdata[152]~input0  = avm_local_bb1_ld__u0_inst0_readdata[152];

assign \avm_local_bb1_ld__u0_inst0_readdata[170]~input0  = avm_local_bb1_ld__u0_inst0_readdata[170];

assign \avm_local_bb1_ld__u0_inst0_readdata[171]~input0  = avm_local_bb1_ld__u0_inst0_readdata[171];

assign \avm_local_bb1_ld__u0_inst0_readdata[172]~input0  = avm_local_bb1_ld__u0_inst0_readdata[172];

assign \avm_local_bb1_ld__u0_inst0_readdata[173]~input0  = avm_local_bb1_ld__u0_inst0_readdata[173];

assign \avm_local_bb1_ld__u0_inst0_readdata[184]~input0  = avm_local_bb1_ld__u0_inst0_readdata[184];

assign \avm_local_bb1_ld__u0_inst0_readdata[202]~input0  = avm_local_bb1_ld__u0_inst0_readdata[202];

assign \avm_local_bb1_ld__u0_inst0_readdata[203]~input0  = avm_local_bb1_ld__u0_inst0_readdata[203];

assign \avm_local_bb1_ld__u0_inst0_readdata[204]~input0  = avm_local_bb1_ld__u0_inst0_readdata[204];

assign \avm_local_bb1_ld__u0_inst0_readdata[205]~input0  = avm_local_bb1_ld__u0_inst0_readdata[205];

assign \avm_local_bb1_ld__u0_inst0_readdata[216]~input0  = avm_local_bb1_ld__u0_inst0_readdata[216];

assign \avm_local_bb1_ld__u0_inst0_readdata[234]~input0  = avm_local_bb1_ld__u0_inst0_readdata[234];

assign \avm_local_bb1_ld__u0_inst0_readdata[235]~input0  = avm_local_bb1_ld__u0_inst0_readdata[235];

assign \avm_local_bb1_ld__u0_inst0_readdata[236]~input0  = avm_local_bb1_ld__u0_inst0_readdata[236];

assign \avm_local_bb1_ld__u0_inst0_readdata[237]~input0  = avm_local_bb1_ld__u0_inst0_readdata[237];

assign \avm_local_bb1_ld__u0_inst0_readdata[248]~input0  = avm_local_bb1_ld__u0_inst0_readdata[248];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[10]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[10] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_first_bit_number = 10;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a10 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[11]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[11] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_first_bit_number = 11;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a11 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[12]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[12] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_first_bit_number = 12;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a12 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[13]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[13] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_first_bit_number = 13;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a13 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[24]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[24] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_first_bit_number = 24;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a24 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[42]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[42] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a42 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[43]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[43] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a43 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[44]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[44] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a44 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[45]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[45] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a45 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[56]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[56] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a56 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[74]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[74] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a74 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[75]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[75] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a75 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[76]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[76] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a76 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[77]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[77] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a77 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[88]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[88] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a88 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[106]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[106] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a106 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[107]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[107] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a107 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[108]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[108] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a108 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[109]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[109] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a109 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[120]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[120] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a120 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[138]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[138] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a138 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[139]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[139] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a139 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[140]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[140] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a140 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[141]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[141] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a141 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[152]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[152] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a152 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[170]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[170] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a170 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[171]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[171] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a171 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[172]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[172] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a172 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[173]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[173] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a173 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[184]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[184] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a184 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[202]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[202] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a202 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[203]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[203] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a203 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[204]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[204] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_first_bit_number = 204;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_first_bit_number = 204;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a204 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[205]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[205] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_first_bit_number = 205;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_first_bit_number = 205;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a205 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[216]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[216] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_first_bit_number = 216;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_first_bit_number = 216;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a216 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[234]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[234] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_first_bit_number = 234;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_first_bit_number = 234;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a234 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[235]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[235] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_first_bit_number = 235;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_first_bit_number = 235;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a235 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[236]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[236] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_first_bit_number = 236;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_first_bit_number = 236;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a236 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[237]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[237] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_first_bit_number = 237;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_first_bit_number = 237;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a237 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[248]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[248] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_first_bit_number = 248;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_first_bit_number = 248;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a248 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[248] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[216] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[184] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[152] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~57_I .lut_mask = "030311DDCFCF11DD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[88] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[120] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[56] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~58_I .lut_mask = "04158C9D2637AEBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~57 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~58 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59_I .lut_mask = "0F0F0F0F55555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~59 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[24] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .lut_mask = "50505F5F03F303F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .lut_mask = "0055FF550F330F33";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[21] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .lut_mask = "1B1B1B1B0055AAFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .lut_mask = "110311CFDD03DDCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .lut_mask = "1B1B1B1B1B1B1B1B";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[18] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__inst0_readdata[17]~input0  = avm_local_bb1_ld__inst0_readdata[17];

assign \avm_local_bb1_ld__inst0_readdata[19]~input0  = avm_local_bb1_ld__inst0_readdata[19];

assign \avm_local_bb1_ld__inst0_readdata[20]~input0  = avm_local_bb1_ld__inst0_readdata[20];

assign \avm_local_bb1_ld__inst0_readdata[25]~input0  = avm_local_bb1_ld__inst0_readdata[25];

assign \avm_local_bb1_ld__inst0_readdata[26]~input0  = avm_local_bb1_ld__inst0_readdata[26];

assign \avm_local_bb1_ld__inst0_readdata[49]~input0  = avm_local_bb1_ld__inst0_readdata[49];

assign \avm_local_bb1_ld__inst0_readdata[51]~input0  = avm_local_bb1_ld__inst0_readdata[51];

assign \avm_local_bb1_ld__inst0_readdata[52]~input0  = avm_local_bb1_ld__inst0_readdata[52];

assign \avm_local_bb1_ld__inst0_readdata[57]~input0  = avm_local_bb1_ld__inst0_readdata[57];

assign \avm_local_bb1_ld__inst0_readdata[58]~input0  = avm_local_bb1_ld__inst0_readdata[58];

assign \avm_local_bb1_ld__inst0_readdata[81]~input0  = avm_local_bb1_ld__inst0_readdata[81];

assign \avm_local_bb1_ld__inst0_readdata[83]~input0  = avm_local_bb1_ld__inst0_readdata[83];

assign \avm_local_bb1_ld__inst0_readdata[84]~input0  = avm_local_bb1_ld__inst0_readdata[84];

assign \avm_local_bb1_ld__inst0_readdata[89]~input0  = avm_local_bb1_ld__inst0_readdata[89];

assign \avm_local_bb1_ld__inst0_readdata[90]~input0  = avm_local_bb1_ld__inst0_readdata[90];

assign \avm_local_bb1_ld__inst0_readdata[113]~input0  = avm_local_bb1_ld__inst0_readdata[113];

assign \avm_local_bb1_ld__inst0_readdata[115]~input0  = avm_local_bb1_ld__inst0_readdata[115];

assign \avm_local_bb1_ld__inst0_readdata[116]~input0  = avm_local_bb1_ld__inst0_readdata[116];

assign \avm_local_bb1_ld__inst0_readdata[121]~input0  = avm_local_bb1_ld__inst0_readdata[121];

assign \avm_local_bb1_ld__inst0_readdata[122]~input0  = avm_local_bb1_ld__inst0_readdata[122];

assign \avm_local_bb1_ld__inst0_readdata[145]~input0  = avm_local_bb1_ld__inst0_readdata[145];

assign \avm_local_bb1_ld__inst0_readdata[147]~input0  = avm_local_bb1_ld__inst0_readdata[147];

assign \avm_local_bb1_ld__inst0_readdata[148]~input0  = avm_local_bb1_ld__inst0_readdata[148];

assign \avm_local_bb1_ld__inst0_readdata[153]~input0  = avm_local_bb1_ld__inst0_readdata[153];

assign \avm_local_bb1_ld__inst0_readdata[154]~input0  = avm_local_bb1_ld__inst0_readdata[154];

assign \avm_local_bb1_ld__inst0_readdata[177]~input0  = avm_local_bb1_ld__inst0_readdata[177];

assign \avm_local_bb1_ld__inst0_readdata[179]~input0  = avm_local_bb1_ld__inst0_readdata[179];

assign \avm_local_bb1_ld__inst0_readdata[180]~input0  = avm_local_bb1_ld__inst0_readdata[180];

assign \avm_local_bb1_ld__inst0_readdata[185]~input0  = avm_local_bb1_ld__inst0_readdata[185];

assign \avm_local_bb1_ld__inst0_readdata[186]~input0  = avm_local_bb1_ld__inst0_readdata[186];

assign \avm_local_bb1_ld__inst0_readdata[209]~input0  = avm_local_bb1_ld__inst0_readdata[209];

assign \avm_local_bb1_ld__inst0_readdata[211]~input0  = avm_local_bb1_ld__inst0_readdata[211];

assign \avm_local_bb1_ld__inst0_readdata[212]~input0  = avm_local_bb1_ld__inst0_readdata[212];

assign \avm_local_bb1_ld__inst0_readdata[217]~input0  = avm_local_bb1_ld__inst0_readdata[217];

assign \avm_local_bb1_ld__inst0_readdata[218]~input0  = avm_local_bb1_ld__inst0_readdata[218];

assign \avm_local_bb1_ld__inst0_readdata[241]~input0  = avm_local_bb1_ld__inst0_readdata[241];

assign \avm_local_bb1_ld__inst0_readdata[243]~input0  = avm_local_bb1_ld__inst0_readdata[243];

assign \avm_local_bb1_ld__inst0_readdata[244]~input0  = avm_local_bb1_ld__inst0_readdata[244];

assign \avm_local_bb1_ld__inst0_readdata[249]~input0  = avm_local_bb1_ld__inst0_readdata[249];

assign \avm_local_bb1_ld__inst0_readdata[250]~input0  = avm_local_bb1_ld__inst0_readdata[250];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[17]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[19]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[20]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[25]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[26]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[49]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[51]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[52]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[57]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[58]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[81]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[83]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[84]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[89]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[90]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[113]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[115]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[116]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[121]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[122]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[145]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[147]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[148]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[153]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[154]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[177]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[179]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[180]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[185]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[186]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[209]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_first_bit_number = 209;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_first_bit_number = 209;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[211]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_first_bit_number = 211;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_first_bit_number = 211;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[212]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_first_bit_number = 212;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_first_bit_number = 212;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[217]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_first_bit_number = 217;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_first_bit_number = 217;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[218]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_first_bit_number = 218;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_first_bit_number = 218;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[241]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_first_bit_number = 241;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_first_bit_number = 241;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[243]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_first_bit_number = 243;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_first_bit_number = 243;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[244]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_first_bit_number = 244;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_first_bit_number = 244;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[249]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_first_bit_number = 249;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_first_bit_number = 249;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[250]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_first_bit_number = 250;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_first_bit_number = 250;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .lut_mask = "4747474700CC33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .lut_mask = "110C113FDD0CDD3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE_I .created_from = "Q(local_bb1_ld__NO_SHIFT_REG[19])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[19] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .lut_mask = "0505F5F5303F303F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .lut_mask = "000FFF0F33553355";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .lut_mask = "00003333CCCCFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[20] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__u0_inst0_readdata[17]~input0  = avm_local_bb1_ld__u0_inst0_readdata[17];

assign \avm_local_bb1_ld__u0_inst0_readdata[19]~input0  = avm_local_bb1_ld__u0_inst0_readdata[19];

assign \avm_local_bb1_ld__u0_inst0_readdata[20]~input0  = avm_local_bb1_ld__u0_inst0_readdata[20];

assign \avm_local_bb1_ld__u0_inst0_readdata[25]~input0  = avm_local_bb1_ld__u0_inst0_readdata[25];

assign \avm_local_bb1_ld__u0_inst0_readdata[26]~input0  = avm_local_bb1_ld__u0_inst0_readdata[26];

assign \avm_local_bb1_ld__u0_inst0_readdata[49]~input0  = avm_local_bb1_ld__u0_inst0_readdata[49];

assign \avm_local_bb1_ld__u0_inst0_readdata[51]~input0  = avm_local_bb1_ld__u0_inst0_readdata[51];

assign \avm_local_bb1_ld__u0_inst0_readdata[52]~input0  = avm_local_bb1_ld__u0_inst0_readdata[52];

assign \avm_local_bb1_ld__u0_inst0_readdata[57]~input0  = avm_local_bb1_ld__u0_inst0_readdata[57];

assign \avm_local_bb1_ld__u0_inst0_readdata[58]~input0  = avm_local_bb1_ld__u0_inst0_readdata[58];

assign \avm_local_bb1_ld__u0_inst0_readdata[81]~input0  = avm_local_bb1_ld__u0_inst0_readdata[81];

assign \avm_local_bb1_ld__u0_inst0_readdata[83]~input0  = avm_local_bb1_ld__u0_inst0_readdata[83];

assign \avm_local_bb1_ld__u0_inst0_readdata[84]~input0  = avm_local_bb1_ld__u0_inst0_readdata[84];

assign \avm_local_bb1_ld__u0_inst0_readdata[89]~input0  = avm_local_bb1_ld__u0_inst0_readdata[89];

assign \avm_local_bb1_ld__u0_inst0_readdata[90]~input0  = avm_local_bb1_ld__u0_inst0_readdata[90];

assign \avm_local_bb1_ld__u0_inst0_readdata[113]~input0  = avm_local_bb1_ld__u0_inst0_readdata[113];

assign \avm_local_bb1_ld__u0_inst0_readdata[115]~input0  = avm_local_bb1_ld__u0_inst0_readdata[115];

assign \avm_local_bb1_ld__u0_inst0_readdata[116]~input0  = avm_local_bb1_ld__u0_inst0_readdata[116];

assign \avm_local_bb1_ld__u0_inst0_readdata[121]~input0  = avm_local_bb1_ld__u0_inst0_readdata[121];

assign \avm_local_bb1_ld__u0_inst0_readdata[122]~input0  = avm_local_bb1_ld__u0_inst0_readdata[122];

assign \avm_local_bb1_ld__u0_inst0_readdata[145]~input0  = avm_local_bb1_ld__u0_inst0_readdata[145];

assign \avm_local_bb1_ld__u0_inst0_readdata[147]~input0  = avm_local_bb1_ld__u0_inst0_readdata[147];

assign \avm_local_bb1_ld__u0_inst0_readdata[148]~input0  = avm_local_bb1_ld__u0_inst0_readdata[148];

assign \avm_local_bb1_ld__u0_inst0_readdata[153]~input0  = avm_local_bb1_ld__u0_inst0_readdata[153];

assign \avm_local_bb1_ld__u0_inst0_readdata[154]~input0  = avm_local_bb1_ld__u0_inst0_readdata[154];

assign \avm_local_bb1_ld__u0_inst0_readdata[177]~input0  = avm_local_bb1_ld__u0_inst0_readdata[177];

assign \avm_local_bb1_ld__u0_inst0_readdata[179]~input0  = avm_local_bb1_ld__u0_inst0_readdata[179];

assign \avm_local_bb1_ld__u0_inst0_readdata[180]~input0  = avm_local_bb1_ld__u0_inst0_readdata[180];

assign \avm_local_bb1_ld__u0_inst0_readdata[185]~input0  = avm_local_bb1_ld__u0_inst0_readdata[185];

assign \avm_local_bb1_ld__u0_inst0_readdata[186]~input0  = avm_local_bb1_ld__u0_inst0_readdata[186];

assign \avm_local_bb1_ld__u0_inst0_readdata[209]~input0  = avm_local_bb1_ld__u0_inst0_readdata[209];

assign \avm_local_bb1_ld__u0_inst0_readdata[211]~input0  = avm_local_bb1_ld__u0_inst0_readdata[211];

assign \avm_local_bb1_ld__u0_inst0_readdata[212]~input0  = avm_local_bb1_ld__u0_inst0_readdata[212];

assign \avm_local_bb1_ld__u0_inst0_readdata[217]~input0  = avm_local_bb1_ld__u0_inst0_readdata[217];

assign \avm_local_bb1_ld__u0_inst0_readdata[218]~input0  = avm_local_bb1_ld__u0_inst0_readdata[218];

assign \avm_local_bb1_ld__u0_inst0_readdata[241]~input0  = avm_local_bb1_ld__u0_inst0_readdata[241];

assign \avm_local_bb1_ld__u0_inst0_readdata[243]~input0  = avm_local_bb1_ld__u0_inst0_readdata[243];

assign \avm_local_bb1_ld__u0_inst0_readdata[244]~input0  = avm_local_bb1_ld__u0_inst0_readdata[244];

assign \avm_local_bb1_ld__u0_inst0_readdata[249]~input0  = avm_local_bb1_ld__u0_inst0_readdata[249];

assign \avm_local_bb1_ld__u0_inst0_readdata[250]~input0  = avm_local_bb1_ld__u0_inst0_readdata[250];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[17]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[17] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_first_bit_number = 17;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a17 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[19]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[19] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_first_bit_number = 19;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a19 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[20]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[20] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_first_bit_number = 20;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a20 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[25]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[25] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_first_bit_number = 25;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a25 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[26]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[26] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_first_bit_number = 26;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a26 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[49]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[49] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a49 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[51]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[51] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a51 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[52]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[52] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a52 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[57]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[57] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a57 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[58]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[58] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a58 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[81]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[81] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a81 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[83]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[83] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a83 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[84]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[84] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a84 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[89]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[89] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a89 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[90]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[90] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a90 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[113]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[113] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a113 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[115]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[115] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a115 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[116]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[116] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a116 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[121]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[121] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a121 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[122]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[122] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a122 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[145]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[145] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a145 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[147]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[147] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a147 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[148]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[148] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a148 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[153]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[153] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a153 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[154]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[154] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a154 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[177]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[177] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a177 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[179]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[179] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a179 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[180]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[180] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a180 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[185]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[185] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a185 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[186]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[186] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a186 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[209]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[209] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_first_bit_number = 209;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_first_bit_number = 209;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a209 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[211]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[211] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_first_bit_number = 211;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_first_bit_number = 211;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a211 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[212]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[212] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_first_bit_number = 212;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_first_bit_number = 212;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a212 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[217]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[217] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_first_bit_number = 217;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_first_bit_number = 217;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a217 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[218]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[218] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_first_bit_number = 218;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_first_bit_number = 218;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a218 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[241]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[241] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_first_bit_number = 241;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_first_bit_number = 241;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a241 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[243]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[243] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_first_bit_number = 243;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_first_bit_number = 243;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a243 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[244]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[244] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_first_bit_number = 244;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_first_bit_number = 244;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a244 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[249]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[249] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_first_bit_number = 249;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_first_bit_number = 249;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a249 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[250]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[250] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_first_bit_number = 250;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_first_bit_number = 250;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a250 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[52] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[84] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[20] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[116] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~82_I .lut_mask = "03F303F350505F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[180] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[212] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[244] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[148] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~81_I .lut_mask = "1111BBBB0A5F0A5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~82 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~81 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~83 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[20] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[51] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[115] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[83] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~79_I .lut_mask = "44440C3F77770C3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[179] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[147] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[211] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[243] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~78_I .lut_mask = "33330F0F555500FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~79 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~78 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~80 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[19] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~2_I .lut_mask = "C00CC00C30033003";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[178] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[210] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[242] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[146] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~66_I .lut_mask = "101C131FD0DCD3DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[50] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[82] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[114] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~67_I .lut_mask = "11110C3FDDDD0C3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~66 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~67 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~68 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE_I .created_from = "Q(local_bb1_ld__NO_SHIFT_REG[18])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[18]~DUPLICATE ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .lut_mask = "00334747CCFF4747";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .lut_mask = "3535000F3535F0FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[16] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .lut_mask = "33330F0F555500FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .lut_mask = "440344CF770377CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[17] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[48] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[112] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[80] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~73_I .lut_mask = "050305F3F503F5F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[208] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[176] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[144] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[240] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~72_I .lut_mask = "03F303F350505F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~73 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~72 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~74 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[16] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[209] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[145] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[241] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[177] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~75_I .lut_mask = "1D1D1D1D0033CCFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[49] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[113] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[81] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~76_I .lut_mask = "0503F50305F3F5F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~75 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~76 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~77 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[17] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~1_I .lut_mask = "8421842184218421";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[181] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[245] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[149] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[213] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~69_I .lut_mask = "11DD030311DDCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[21] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[53] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[117] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[85] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~70_I .lut_mask = "5353000F5353F0FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~69 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~70 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~71 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[21] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~3_I .lut_mask = "0000080200000401";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~4_I .lut_mask = "0000000050055005";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .lut_mask = "0055FF55330F330F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .lut_mask = "1015B0B51A1FBABF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[25] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[89] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[57] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[25] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[121] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~88_I .lut_mask = "0344CF440377CF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[153] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[249] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[217] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[185] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~87_I .lut_mask = "4403770344CF77CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~88 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~87 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89_I .lut_mask = "50505F5F50505F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~89 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[25] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .lut_mask = "00334747CCFF4747";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .lut_mask = "03CF03CF1111DDDD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[26] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[218] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[186] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[154] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[250] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~84_I .lut_mask = "0522AF220577AF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[26] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[122] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[90] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[58] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~85_I .lut_mask = "550F550F0033FF33";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~84 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~85 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86_I .lut_mask = "00003333CCCCFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~86 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[26] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~7_I .lut_mask = "4F4F4F4F04040404";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .lut_mask = "00CC1D1D33FF1D1D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .lut_mask = "270027AA275527FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[15] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .lut_mask = "0F0F555500FF3333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .lut_mask = "051105BBAF11AFBB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[14] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:GEN_WORD_OFFSET_FIFO.offset_fifo|scfifo_0pc1:auto_generated|a_dpfifo_maa1:dpfifo|altsyncram_fhn1:FIFOram|q_b[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|offset_stall~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|R_offset[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[110] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[46] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[78] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~13_I .lut_mask = "0F330F330055FF55";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[174] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[238] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[142] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[206] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~12_I .lut_mask = "0027AA275527FF27";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~13 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~12 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~14 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[14] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__u0_inst0_readdata[5]~input0  = avm_local_bb1_ld__u0_inst0_readdata[5];

assign \avm_local_bb1_ld__u0_inst0_readdata[6]~input0  = avm_local_bb1_ld__u0_inst0_readdata[6];

assign \avm_local_bb1_ld__u0_inst0_readdata[7]~input0  = avm_local_bb1_ld__u0_inst0_readdata[7];

assign \avm_local_bb1_ld__u0_inst0_readdata[8]~input0  = avm_local_bb1_ld__u0_inst0_readdata[8];

assign \avm_local_bb1_ld__u0_inst0_readdata[9]~input0  = avm_local_bb1_ld__u0_inst0_readdata[9];

assign \avm_local_bb1_ld__u0_inst0_readdata[37]~input0  = avm_local_bb1_ld__u0_inst0_readdata[37];

assign \avm_local_bb1_ld__u0_inst0_readdata[38]~input0  = avm_local_bb1_ld__u0_inst0_readdata[38];

assign \avm_local_bb1_ld__u0_inst0_readdata[39]~input0  = avm_local_bb1_ld__u0_inst0_readdata[39];

assign \avm_local_bb1_ld__u0_inst0_readdata[40]~input0  = avm_local_bb1_ld__u0_inst0_readdata[40];

assign \avm_local_bb1_ld__u0_inst0_readdata[41]~input0  = avm_local_bb1_ld__u0_inst0_readdata[41];

assign \avm_local_bb1_ld__u0_inst0_readdata[69]~input0  = avm_local_bb1_ld__u0_inst0_readdata[69];

assign \avm_local_bb1_ld__u0_inst0_readdata[70]~input0  = avm_local_bb1_ld__u0_inst0_readdata[70];

assign \avm_local_bb1_ld__u0_inst0_readdata[71]~input0  = avm_local_bb1_ld__u0_inst0_readdata[71];

assign \avm_local_bb1_ld__u0_inst0_readdata[72]~input0  = avm_local_bb1_ld__u0_inst0_readdata[72];

assign \avm_local_bb1_ld__u0_inst0_readdata[73]~input0  = avm_local_bb1_ld__u0_inst0_readdata[73];

assign \avm_local_bb1_ld__u0_inst0_readdata[101]~input0  = avm_local_bb1_ld__u0_inst0_readdata[101];

assign \avm_local_bb1_ld__u0_inst0_readdata[102]~input0  = avm_local_bb1_ld__u0_inst0_readdata[102];

assign \avm_local_bb1_ld__u0_inst0_readdata[103]~input0  = avm_local_bb1_ld__u0_inst0_readdata[103];

assign \avm_local_bb1_ld__u0_inst0_readdata[104]~input0  = avm_local_bb1_ld__u0_inst0_readdata[104];

assign \avm_local_bb1_ld__u0_inst0_readdata[105]~input0  = avm_local_bb1_ld__u0_inst0_readdata[105];

assign \avm_local_bb1_ld__u0_inst0_readdata[133]~input0  = avm_local_bb1_ld__u0_inst0_readdata[133];

assign \avm_local_bb1_ld__u0_inst0_readdata[134]~input0  = avm_local_bb1_ld__u0_inst0_readdata[134];

assign \avm_local_bb1_ld__u0_inst0_readdata[135]~input0  = avm_local_bb1_ld__u0_inst0_readdata[135];

assign \avm_local_bb1_ld__u0_inst0_readdata[136]~input0  = avm_local_bb1_ld__u0_inst0_readdata[136];

assign \avm_local_bb1_ld__u0_inst0_readdata[137]~input0  = avm_local_bb1_ld__u0_inst0_readdata[137];

assign \avm_local_bb1_ld__u0_inst0_readdata[165]~input0  = avm_local_bb1_ld__u0_inst0_readdata[165];

assign \avm_local_bb1_ld__u0_inst0_readdata[166]~input0  = avm_local_bb1_ld__u0_inst0_readdata[166];

assign \avm_local_bb1_ld__u0_inst0_readdata[167]~input0  = avm_local_bb1_ld__u0_inst0_readdata[167];

assign \avm_local_bb1_ld__u0_inst0_readdata[168]~input0  = avm_local_bb1_ld__u0_inst0_readdata[168];

assign \avm_local_bb1_ld__u0_inst0_readdata[169]~input0  = avm_local_bb1_ld__u0_inst0_readdata[169];

assign \avm_local_bb1_ld__u0_inst0_readdata[197]~input0  = avm_local_bb1_ld__u0_inst0_readdata[197];

assign \avm_local_bb1_ld__u0_inst0_readdata[198]~input0  = avm_local_bb1_ld__u0_inst0_readdata[198];

assign \avm_local_bb1_ld__u0_inst0_readdata[199]~input0  = avm_local_bb1_ld__u0_inst0_readdata[199];

assign \avm_local_bb1_ld__u0_inst0_readdata[200]~input0  = avm_local_bb1_ld__u0_inst0_readdata[200];

assign \avm_local_bb1_ld__u0_inst0_readdata[201]~input0  = avm_local_bb1_ld__u0_inst0_readdata[201];

assign \avm_local_bb1_ld__u0_inst0_readdata[229]~input0  = avm_local_bb1_ld__u0_inst0_readdata[229];

assign \avm_local_bb1_ld__u0_inst0_readdata[230]~input0  = avm_local_bb1_ld__u0_inst0_readdata[230];

assign \avm_local_bb1_ld__u0_inst0_readdata[231]~input0  = avm_local_bb1_ld__u0_inst0_readdata[231];

assign \avm_local_bb1_ld__u0_inst0_readdata[232]~input0  = avm_local_bb1_ld__u0_inst0_readdata[232];

assign \avm_local_bb1_ld__u0_inst0_readdata[233]~input0  = avm_local_bb1_ld__u0_inst0_readdata[233];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[5]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[6]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[7]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[8]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[9]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[37]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[38]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[39]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[40]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[41]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[69]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[70]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[71]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[72]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[73]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[101]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[102]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[103]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[104]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[105]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[133]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[134]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[135]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[136]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[137]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[165]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[166]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[167]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[168]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[169]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[197]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[198]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[199]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[200]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[201]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[229]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_first_bit_number = 229;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_first_bit_number = 229;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[230]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_first_bit_number = 230;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_first_bit_number = 230;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[231]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_first_bit_number = 231;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_first_bit_number = 231;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[232]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_first_bit_number = 232;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_first_bit_number = 232;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[233]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_first_bit_number = 233;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_first_bit_number = 233;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .lut_mask = "470047CC473347FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .lut_mask = "08194C5D2A3B6E7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .lut_mask = "00000F0FFFFF0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[9] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .lut_mask = "11DD030311DDCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .lut_mask = "0511AF1105BBAFBB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .lut_mask = "0F0F00000F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[10] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .lut_mask = "03440377CF44CF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .lut_mask = "553355330F000FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[11] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[234] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[138] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[170] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[202] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~48_I .lut_mask = "01A10BAB51F15BFB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[74] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[106] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[42] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~49_I .lut_mask = "000F5353F0FF5353";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~48 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~49 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~50 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[10] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[107] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[43] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[75] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~46_I .lut_mask = "0F3300550F33FF55";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[235] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[171] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[139] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[203] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~45_I .lut_mask = "05AF111105AFBBBB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~46 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~45 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47_I .lut_mask = "00CC00CC33FF33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~47 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[11] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~5_I .lut_mask = "7733773311001100";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .lut_mask = "041526378C9DAEBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .lut_mask = "207025752A7A2F7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[13] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .lut_mask = "04340737C4F4C7F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .lut_mask = "0027AA275527FF27";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .lut_mask = "00550055AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE_I .created_from = "Q(local_bb1_ld__u0_NO_SHIFT_REG[12])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[12]~DUPLICATE ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[204] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[172] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[236] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[140] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~54_I .lut_mask = "05220577AF22AF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[108] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[12] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[44] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[76] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~55_I .lut_mask = "01A151F10BAB5BFB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~54 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~55 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56_I .lut_mask = "00003333CCCCFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~56 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[12] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[237] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[173] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[141] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[205] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~51_I .lut_mask = "010DC1CD313DF1FD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[45] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[13] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[109] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[77] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~52_I .lut_mask = "333300FF55550F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~51 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~52 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~53 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[13] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~6_I .lut_mask = "A00AA00A50055005";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~4_I .lut_mask = "8484848421212121";

assign \avm_local_bb1_ld__inst0_readdata[5]~input0  = avm_local_bb1_ld__inst0_readdata[5];

assign \avm_local_bb1_ld__inst0_readdata[6]~input0  = avm_local_bb1_ld__inst0_readdata[6];

assign \avm_local_bb1_ld__inst0_readdata[7]~input0  = avm_local_bb1_ld__inst0_readdata[7];

assign \avm_local_bb1_ld__inst0_readdata[8]~input0  = avm_local_bb1_ld__inst0_readdata[8];

assign \avm_local_bb1_ld__inst0_readdata[9]~input0  = avm_local_bb1_ld__inst0_readdata[9];

assign \avm_local_bb1_ld__inst0_readdata[37]~input0  = avm_local_bb1_ld__inst0_readdata[37];

assign \avm_local_bb1_ld__inst0_readdata[38]~input0  = avm_local_bb1_ld__inst0_readdata[38];

assign \avm_local_bb1_ld__inst0_readdata[39]~input0  = avm_local_bb1_ld__inst0_readdata[39];

assign \avm_local_bb1_ld__inst0_readdata[40]~input0  = avm_local_bb1_ld__inst0_readdata[40];

assign \avm_local_bb1_ld__inst0_readdata[41]~input0  = avm_local_bb1_ld__inst0_readdata[41];

assign \avm_local_bb1_ld__inst0_readdata[69]~input0  = avm_local_bb1_ld__inst0_readdata[69];

assign \avm_local_bb1_ld__inst0_readdata[70]~input0  = avm_local_bb1_ld__inst0_readdata[70];

assign \avm_local_bb1_ld__inst0_readdata[71]~input0  = avm_local_bb1_ld__inst0_readdata[71];

assign \avm_local_bb1_ld__inst0_readdata[72]~input0  = avm_local_bb1_ld__inst0_readdata[72];

assign \avm_local_bb1_ld__inst0_readdata[73]~input0  = avm_local_bb1_ld__inst0_readdata[73];

assign \avm_local_bb1_ld__inst0_readdata[101]~input0  = avm_local_bb1_ld__inst0_readdata[101];

assign \avm_local_bb1_ld__inst0_readdata[102]~input0  = avm_local_bb1_ld__inst0_readdata[102];

assign \avm_local_bb1_ld__inst0_readdata[103]~input0  = avm_local_bb1_ld__inst0_readdata[103];

assign \avm_local_bb1_ld__inst0_readdata[104]~input0  = avm_local_bb1_ld__inst0_readdata[104];

assign \avm_local_bb1_ld__inst0_readdata[105]~input0  = avm_local_bb1_ld__inst0_readdata[105];

assign \avm_local_bb1_ld__inst0_readdata[133]~input0  = avm_local_bb1_ld__inst0_readdata[133];

assign \avm_local_bb1_ld__inst0_readdata[134]~input0  = avm_local_bb1_ld__inst0_readdata[134];

assign \avm_local_bb1_ld__inst0_readdata[135]~input0  = avm_local_bb1_ld__inst0_readdata[135];

assign \avm_local_bb1_ld__inst0_readdata[136]~input0  = avm_local_bb1_ld__inst0_readdata[136];

assign \avm_local_bb1_ld__inst0_readdata[137]~input0  = avm_local_bb1_ld__inst0_readdata[137];

assign \avm_local_bb1_ld__inst0_readdata[165]~input0  = avm_local_bb1_ld__inst0_readdata[165];

assign \avm_local_bb1_ld__inst0_readdata[166]~input0  = avm_local_bb1_ld__inst0_readdata[166];

assign \avm_local_bb1_ld__inst0_readdata[167]~input0  = avm_local_bb1_ld__inst0_readdata[167];

assign \avm_local_bb1_ld__inst0_readdata[168]~input0  = avm_local_bb1_ld__inst0_readdata[168];

assign \avm_local_bb1_ld__inst0_readdata[169]~input0  = avm_local_bb1_ld__inst0_readdata[169];

assign \avm_local_bb1_ld__inst0_readdata[197]~input0  = avm_local_bb1_ld__inst0_readdata[197];

assign \avm_local_bb1_ld__inst0_readdata[198]~input0  = avm_local_bb1_ld__inst0_readdata[198];

assign \avm_local_bb1_ld__inst0_readdata[199]~input0  = avm_local_bb1_ld__inst0_readdata[199];

assign \avm_local_bb1_ld__inst0_readdata[200]~input0  = avm_local_bb1_ld__inst0_readdata[200];

assign \avm_local_bb1_ld__inst0_readdata[201]~input0  = avm_local_bb1_ld__inst0_readdata[201];

assign \avm_local_bb1_ld__inst0_readdata[229]~input0  = avm_local_bb1_ld__inst0_readdata[229];

assign \avm_local_bb1_ld__inst0_readdata[230]~input0  = avm_local_bb1_ld__inst0_readdata[230];

assign \avm_local_bb1_ld__inst0_readdata[231]~input0  = avm_local_bb1_ld__inst0_readdata[231];

assign \avm_local_bb1_ld__inst0_readdata[232]~input0  = avm_local_bb1_ld__inst0_readdata[232];

assign \avm_local_bb1_ld__inst0_readdata[233]~input0  = avm_local_bb1_ld__inst0_readdata[233];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[5]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[5] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_first_bit_number = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a5 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[6]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[6] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_first_bit_number = 6;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a6 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[7]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[7] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_first_bit_number = 7;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a7 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[8]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[8] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_first_bit_number = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a8 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[9]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[9] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_first_bit_number = 9;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a9 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[37]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[37] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a37 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[38]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[38] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a38 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[39]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[39] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a39 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[40]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[40] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a40 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[41]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[41] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a41 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[69]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[69] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a69 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[70]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[70] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a70 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[71]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[71] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a71 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[72]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[72] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a72 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[73]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[73] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a73 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[101]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[101] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a101 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[102]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[102] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a102 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[103]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[103] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a103 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[104]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[104] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a104 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[105]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[105] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a105 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[133]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[133] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a133 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[134]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[134] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a134 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[135]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[135] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a135 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[136]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[136] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a136 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[137]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[137] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a137 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[165]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[165] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a165 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[166]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[166] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a166 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[167]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[167] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a167 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[168]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[168] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a168 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[169]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[169] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a169 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[197]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[197] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a197 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[198]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[198] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a198 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[199]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[199] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a199 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[200]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[200] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a200 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[201]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[201] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a201 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[229]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[229] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_first_bit_number = 229;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_first_bit_number = 229;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a229 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[230]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[230] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_first_bit_number = 230;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_first_bit_number = 230;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a230 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[231]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[231] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_first_bit_number = 231;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_first_bit_number = 231;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a231 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[232]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[232] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_first_bit_number = 232;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_first_bit_number = 232;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a232 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[233]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[233] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_first_bit_number = 233;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_first_bit_number = 233;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a233 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[105] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[41] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[73] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~16_I .lut_mask = "010DC1CD313DF1FD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[233] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[201] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[137] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[169] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~15_I .lut_mask = "00CC33FF1D1D1D1D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~16 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~17 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[9] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .lut_mask = "03F303F350505F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .lut_mask = "050305F3F503F5F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .lut_mask = "00330033CCFFCCFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[7] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .lut_mask = "101C131FD0DCD3DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .lut_mask = "5555333300FF0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[8] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[104] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[40] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[72] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~19_I .lut_mask = "440344CF770377CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[232] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[200] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[136] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[168] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~18_I .lut_mask = "001BAA1B551BFF1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~19 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~18 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20_I .lut_mask = "0000CCCC3333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~20 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[8] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[167] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[231] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[199] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[135] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~21_I .lut_mask = "00334747CCFF4747";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[103] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[71] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[39] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~22_I .lut_mask = "00F00FFF35353535";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~21 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~22 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~23_I .lut_mask = "00000F0FF0F0FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~23 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[7] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .lut_mask = "3300550F33FF550F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .lut_mask = "04073437C4C7F4F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .lut_mask = "505050505F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[5] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__u0_inst0_readdata[0]~input0  = avm_local_bb1_ld__u0_inst0_readdata[0];

assign \avm_local_bb1_ld__u0_inst0_readdata[1]~input0  = avm_local_bb1_ld__u0_inst0_readdata[1];

assign \avm_local_bb1_ld__u0_inst0_readdata[2]~input0  = avm_local_bb1_ld__u0_inst0_readdata[2];

assign \avm_local_bb1_ld__u0_inst0_readdata[3]~input0  = avm_local_bb1_ld__u0_inst0_readdata[3];

assign \avm_local_bb1_ld__u0_inst0_readdata[4]~input0  = avm_local_bb1_ld__u0_inst0_readdata[4];

assign \avm_local_bb1_ld__u0_inst0_readdata[32]~input0  = avm_local_bb1_ld__u0_inst0_readdata[32];

assign \avm_local_bb1_ld__u0_inst0_readdata[33]~input0  = avm_local_bb1_ld__u0_inst0_readdata[33];

assign \avm_local_bb1_ld__u0_inst0_readdata[34]~input0  = avm_local_bb1_ld__u0_inst0_readdata[34];

assign \avm_local_bb1_ld__u0_inst0_readdata[35]~input0  = avm_local_bb1_ld__u0_inst0_readdata[35];

assign \avm_local_bb1_ld__u0_inst0_readdata[36]~input0  = avm_local_bb1_ld__u0_inst0_readdata[36];

assign \avm_local_bb1_ld__u0_inst0_readdata[64]~input0  = avm_local_bb1_ld__u0_inst0_readdata[64];

assign \avm_local_bb1_ld__u0_inst0_readdata[65]~input0  = avm_local_bb1_ld__u0_inst0_readdata[65];

assign \avm_local_bb1_ld__u0_inst0_readdata[66]~input0  = avm_local_bb1_ld__u0_inst0_readdata[66];

assign \avm_local_bb1_ld__u0_inst0_readdata[67]~input0  = avm_local_bb1_ld__u0_inst0_readdata[67];

assign \avm_local_bb1_ld__u0_inst0_readdata[68]~input0  = avm_local_bb1_ld__u0_inst0_readdata[68];

assign \avm_local_bb1_ld__u0_inst0_readdata[96]~input0  = avm_local_bb1_ld__u0_inst0_readdata[96];

assign \avm_local_bb1_ld__u0_inst0_readdata[97]~input0  = avm_local_bb1_ld__u0_inst0_readdata[97];

assign \avm_local_bb1_ld__u0_inst0_readdata[98]~input0  = avm_local_bb1_ld__u0_inst0_readdata[98];

assign \avm_local_bb1_ld__u0_inst0_readdata[99]~input0  = avm_local_bb1_ld__u0_inst0_readdata[99];

assign \avm_local_bb1_ld__u0_inst0_readdata[100]~input0  = avm_local_bb1_ld__u0_inst0_readdata[100];

assign \avm_local_bb1_ld__u0_inst0_readdata[128]~input0  = avm_local_bb1_ld__u0_inst0_readdata[128];

assign \avm_local_bb1_ld__u0_inst0_readdata[129]~input0  = avm_local_bb1_ld__u0_inst0_readdata[129];

assign \avm_local_bb1_ld__u0_inst0_readdata[130]~input0  = avm_local_bb1_ld__u0_inst0_readdata[130];

assign \avm_local_bb1_ld__u0_inst0_readdata[131]~input0  = avm_local_bb1_ld__u0_inst0_readdata[131];

assign \avm_local_bb1_ld__u0_inst0_readdata[132]~input0  = avm_local_bb1_ld__u0_inst0_readdata[132];

assign \avm_local_bb1_ld__u0_inst0_readdata[160]~input0  = avm_local_bb1_ld__u0_inst0_readdata[160];

assign \avm_local_bb1_ld__u0_inst0_readdata[161]~input0  = avm_local_bb1_ld__u0_inst0_readdata[161];

assign \avm_local_bb1_ld__u0_inst0_readdata[162]~input0  = avm_local_bb1_ld__u0_inst0_readdata[162];

assign \avm_local_bb1_ld__u0_inst0_readdata[163]~input0  = avm_local_bb1_ld__u0_inst0_readdata[163];

assign \avm_local_bb1_ld__u0_inst0_readdata[164]~input0  = avm_local_bb1_ld__u0_inst0_readdata[164];

assign \avm_local_bb1_ld__u0_inst0_readdata[192]~input0  = avm_local_bb1_ld__u0_inst0_readdata[192];

assign \avm_local_bb1_ld__u0_inst0_readdata[193]~input0  = avm_local_bb1_ld__u0_inst0_readdata[193];

assign \avm_local_bb1_ld__u0_inst0_readdata[194]~input0  = avm_local_bb1_ld__u0_inst0_readdata[194];

assign \avm_local_bb1_ld__u0_inst0_readdata[195]~input0  = avm_local_bb1_ld__u0_inst0_readdata[195];

assign \avm_local_bb1_ld__u0_inst0_readdata[196]~input0  = avm_local_bb1_ld__u0_inst0_readdata[196];

assign \avm_local_bb1_ld__u0_inst0_readdata[224]~input0  = avm_local_bb1_ld__u0_inst0_readdata[224];

assign \avm_local_bb1_ld__u0_inst0_readdata[225]~input0  = avm_local_bb1_ld__u0_inst0_readdata[225];

assign \avm_local_bb1_ld__u0_inst0_readdata[226]~input0  = avm_local_bb1_ld__u0_inst0_readdata[226];

assign \avm_local_bb1_ld__u0_inst0_readdata[227]~input0  = avm_local_bb1_ld__u0_inst0_readdata[227];

assign \avm_local_bb1_ld__u0_inst0_readdata[228]~input0  = avm_local_bb1_ld__u0_inst0_readdata[228];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[0]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[1]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[2]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[3]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[4]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[32]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[33]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[34]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[35]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[36]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[64]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[65]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[66]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[67]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[68]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[96]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[97]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[98]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[99]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[100]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[128]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[129]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[130]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[131]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[132]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[160]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[161]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[162]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[163]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[164]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[192]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[193]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[194]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[195]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[196]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[224]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_first_bit_number = 224;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_first_bit_number = 224;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[225]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_first_bit_number = 225;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_first_bit_number = 225;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[226]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_first_bit_number = 226;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_first_bit_number = 226;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[227]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_first_bit_number = 227;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_first_bit_number = 227;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[228]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_first_bit_number = 228;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_first_bit_number = 228;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .lut_mask = "55330F0055330FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .lut_mask = "111103CFDDDD03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .lut_mask = "0F0F00000F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__inst0_readdata[0]~input0  = avm_local_bb1_ld__inst0_readdata[0];

assign \avm_local_bb1_ld__inst0_readdata[1]~input0  = avm_local_bb1_ld__inst0_readdata[1];

assign \avm_local_bb1_ld__inst0_readdata[2]~input0  = avm_local_bb1_ld__inst0_readdata[2];

assign \avm_local_bb1_ld__inst0_readdata[3]~input0  = avm_local_bb1_ld__inst0_readdata[3];

assign \avm_local_bb1_ld__inst0_readdata[4]~input0  = avm_local_bb1_ld__inst0_readdata[4];

assign \avm_local_bb1_ld__inst0_readdata[32]~input0  = avm_local_bb1_ld__inst0_readdata[32];

assign \avm_local_bb1_ld__inst0_readdata[33]~input0  = avm_local_bb1_ld__inst0_readdata[33];

assign \avm_local_bb1_ld__inst0_readdata[34]~input0  = avm_local_bb1_ld__inst0_readdata[34];

assign \avm_local_bb1_ld__inst0_readdata[35]~input0  = avm_local_bb1_ld__inst0_readdata[35];

assign \avm_local_bb1_ld__inst0_readdata[36]~input0  = avm_local_bb1_ld__inst0_readdata[36];

assign \avm_local_bb1_ld__inst0_readdata[64]~input0  = avm_local_bb1_ld__inst0_readdata[64];

assign \avm_local_bb1_ld__inst0_readdata[65]~input0  = avm_local_bb1_ld__inst0_readdata[65];

assign \avm_local_bb1_ld__inst0_readdata[66]~input0  = avm_local_bb1_ld__inst0_readdata[66];

assign \avm_local_bb1_ld__inst0_readdata[67]~input0  = avm_local_bb1_ld__inst0_readdata[67];

assign \avm_local_bb1_ld__inst0_readdata[68]~input0  = avm_local_bb1_ld__inst0_readdata[68];

assign \avm_local_bb1_ld__inst0_readdata[96]~input0  = avm_local_bb1_ld__inst0_readdata[96];

assign \avm_local_bb1_ld__inst0_readdata[97]~input0  = avm_local_bb1_ld__inst0_readdata[97];

assign \avm_local_bb1_ld__inst0_readdata[98]~input0  = avm_local_bb1_ld__inst0_readdata[98];

assign \avm_local_bb1_ld__inst0_readdata[99]~input0  = avm_local_bb1_ld__inst0_readdata[99];

assign \avm_local_bb1_ld__inst0_readdata[100]~input0  = avm_local_bb1_ld__inst0_readdata[100];

assign \avm_local_bb1_ld__inst0_readdata[128]~input0  = avm_local_bb1_ld__inst0_readdata[128];

assign \avm_local_bb1_ld__inst0_readdata[129]~input0  = avm_local_bb1_ld__inst0_readdata[129];

assign \avm_local_bb1_ld__inst0_readdata[130]~input0  = avm_local_bb1_ld__inst0_readdata[130];

assign \avm_local_bb1_ld__inst0_readdata[131]~input0  = avm_local_bb1_ld__inst0_readdata[131];

assign \avm_local_bb1_ld__inst0_readdata[132]~input0  = avm_local_bb1_ld__inst0_readdata[132];

assign \avm_local_bb1_ld__inst0_readdata[160]~input0  = avm_local_bb1_ld__inst0_readdata[160];

assign \avm_local_bb1_ld__inst0_readdata[161]~input0  = avm_local_bb1_ld__inst0_readdata[161];

assign \avm_local_bb1_ld__inst0_readdata[162]~input0  = avm_local_bb1_ld__inst0_readdata[162];

assign \avm_local_bb1_ld__inst0_readdata[163]~input0  = avm_local_bb1_ld__inst0_readdata[163];

assign \avm_local_bb1_ld__inst0_readdata[164]~input0  = avm_local_bb1_ld__inst0_readdata[164];

assign \avm_local_bb1_ld__inst0_readdata[192]~input0  = avm_local_bb1_ld__inst0_readdata[192];

assign \avm_local_bb1_ld__inst0_readdata[193]~input0  = avm_local_bb1_ld__inst0_readdata[193];

assign \avm_local_bb1_ld__inst0_readdata[194]~input0  = avm_local_bb1_ld__inst0_readdata[194];

assign \avm_local_bb1_ld__inst0_readdata[195]~input0  = avm_local_bb1_ld__inst0_readdata[195];

assign \avm_local_bb1_ld__inst0_readdata[196]~input0  = avm_local_bb1_ld__inst0_readdata[196];

assign \avm_local_bb1_ld__inst0_readdata[224]~input0  = avm_local_bb1_ld__inst0_readdata[224];

assign \avm_local_bb1_ld__inst0_readdata[225]~input0  = avm_local_bb1_ld__inst0_readdata[225];

assign \avm_local_bb1_ld__inst0_readdata[226]~input0  = avm_local_bb1_ld__inst0_readdata[226];

assign \avm_local_bb1_ld__inst0_readdata[227]~input0  = avm_local_bb1_ld__inst0_readdata[227];

assign \avm_local_bb1_ld__inst0_readdata[228]~input0  = avm_local_bb1_ld__inst0_readdata[228];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[0]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[0] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_first_bit_number = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a0 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[1]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[1] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_first_bit_number = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a1 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[2]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[2] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_first_bit_number = 2;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a2 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[3]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[3] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_first_bit_number = 3;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a3 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[4]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[4] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_first_bit_number = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a4 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[32]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[32] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a32 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[33]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[33] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a33 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[34]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[34] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a34 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[35]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[35] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a35 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[36]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[36] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a36 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[64]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[64] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a64 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[65]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[65] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a65 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[66]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[66] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a66 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[67]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[67] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a67 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[68]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[68] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a68 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[96]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[96] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a96 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[97]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[97] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a97 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[98]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[98] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a98 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[99]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[99] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a99 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[100]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[100] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a100 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[128]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[128] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a128 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[129]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[129] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a129 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[130]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[130] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a130 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[131]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[131] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a131 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[132]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[132] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a132 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[160]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[160] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a160 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[161]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[161] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a161 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[162]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[162] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a162 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[163]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[163] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a163 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[164]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[164] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a164 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[192]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[192] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a192 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[193]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[193] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a193 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[194]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[194] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a194 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[195]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[195] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a195 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[196]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[196] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a196 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[224]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[224] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_first_bit_number = 224;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_first_bit_number = 224;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a224 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[225]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[225] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_first_bit_number = 225;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_first_bit_number = 225;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a225 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[226]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[226] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_first_bit_number = 226;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_first_bit_number = 226;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a226 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[227]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[227] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_first_bit_number = 227;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_first_bit_number = 227;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a227 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[228]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[228] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_first_bit_number = 228;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_first_bit_number = 228;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a228 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .lut_mask = "0505303FF5F5303F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .lut_mask = "55550F0F333300FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[0] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .lut_mask = "03F3050503F3F5F5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .lut_mask = "110C113FDD0CDD3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .lut_mask = "33330F0F33330F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[2] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[33] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[97] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[65] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~40_I .lut_mask = "5353000F5353F0FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[161] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[225] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[193] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[129] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~39_I .lut_mask = "041526378C9DAEBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~40 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~39 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~41 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[1] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[64] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[32] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[96] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~43_I .lut_mask = "1B001BAA1B551BFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[160] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[192] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[224] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[128] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~42_I .lut_mask = "02520757A2F2A7F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~43 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~42 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44_I .lut_mask = "50505F5F50505F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~44 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[0] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[34] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[98] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[66] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~37_I .lut_mask = "5300530F53F053FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[162] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[194] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[226] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[130] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~36_I .lut_mask = "0505F5F5303F303F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~37 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~36 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~38 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[2] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~0_I .lut_mask = "5F0FDF4F05000D04";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .lut_mask = "0C440C773F443F77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .lut_mask = "00AA272755FF2727";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[4] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[36] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[68] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[100] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~31_I .lut_mask = "10D01CDC13D31FDF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[132] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[164] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[228] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[196] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~30_I .lut_mask = "555500FF33330F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~31 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~30 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32_I .lut_mask = "333300003333FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~32 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[4] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .lut_mask = "000FFF0F55335533";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .lut_mask = "447703034477CFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[3] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[35] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[99] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[67] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~34_I .lut_mask = "1105BB0511AFBBAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[227] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[131] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[195] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[163] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~33_I .lut_mask = "33330F0F00FF5555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~34 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~33 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~35 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[3] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~1_I .lut_mask = "71F371F330713071";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .lut_mask = "001B551BAA1BFF1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .lut_mask = "01C131F10DCD3DFD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[6] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[165] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[133] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[229] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[197] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~27_I .lut_mask = "0A0A22775F5F2277";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[101] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[37] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[69] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~28_I .lut_mask = "0C0C11DD3F3F11DD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~27 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~28 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~29 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[5] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[230] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[134] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[166] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[198] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~24_I .lut_mask = "0C110CDD3F113FDD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[70] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[38] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[102] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~25_I .lut_mask = "110C113FDD0CDD3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~26 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[6] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~2_I .lut_mask = "70107010F7F1F7F1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~3_I .lut_mask = "0C8E0C8E8ECF8ECF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~5 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~4 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~7_I .lut_mask = "03070303030F0307";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[175] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[143] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[239] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[207] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~9_I .lut_mask = "3030505F3F3F505F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[47] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[111] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[79] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~10_I .lut_mask = "407043734C7C4F7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~11 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[15] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~8_I .lut_mask = "55F555F500500050";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~7 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan0~9_I .lut_mask = "F775511075751010";

assign \avm_local_bb1_ld__u0_inst0_readdata[27]~input0  = avm_local_bb1_ld__u0_inst0_readdata[27];

assign \avm_local_bb1_ld__u0_inst0_readdata[28]~input0  = avm_local_bb1_ld__u0_inst0_readdata[28];

assign \avm_local_bb1_ld__u0_inst0_readdata[59]~input0  = avm_local_bb1_ld__u0_inst0_readdata[59];

assign \avm_local_bb1_ld__u0_inst0_readdata[60]~input0  = avm_local_bb1_ld__u0_inst0_readdata[60];

assign \avm_local_bb1_ld__u0_inst0_readdata[91]~input0  = avm_local_bb1_ld__u0_inst0_readdata[91];

assign \avm_local_bb1_ld__u0_inst0_readdata[92]~input0  = avm_local_bb1_ld__u0_inst0_readdata[92];

assign \avm_local_bb1_ld__u0_inst0_readdata[123]~input0  = avm_local_bb1_ld__u0_inst0_readdata[123];

assign \avm_local_bb1_ld__u0_inst0_readdata[124]~input0  = avm_local_bb1_ld__u0_inst0_readdata[124];

assign \avm_local_bb1_ld__u0_inst0_readdata[155]~input0  = avm_local_bb1_ld__u0_inst0_readdata[155];

assign \avm_local_bb1_ld__u0_inst0_readdata[156]~input0  = avm_local_bb1_ld__u0_inst0_readdata[156];

assign \avm_local_bb1_ld__u0_inst0_readdata[187]~input0  = avm_local_bb1_ld__u0_inst0_readdata[187];

assign \avm_local_bb1_ld__u0_inst0_readdata[188]~input0  = avm_local_bb1_ld__u0_inst0_readdata[188];

assign \avm_local_bb1_ld__u0_inst0_readdata[219]~input0  = avm_local_bb1_ld__u0_inst0_readdata[219];

assign \avm_local_bb1_ld__u0_inst0_readdata[220]~input0  = avm_local_bb1_ld__u0_inst0_readdata[220];

assign \avm_local_bb1_ld__u0_inst0_readdata[251]~input0  = avm_local_bb1_ld__u0_inst0_readdata[251];

assign \avm_local_bb1_ld__u0_inst0_readdata[252]~input0  = avm_local_bb1_ld__u0_inst0_readdata[252];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[27]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[28]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[59]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[60]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[91]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[92]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[123]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[124]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[155]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[156]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[187]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[188]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[219]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_first_bit_number = 219;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_first_bit_number = 219;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[220]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_first_bit_number = 220;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_first_bit_number = 220;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[251]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_first_bit_number = 251;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_first_bit_number = 251;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 (
	.portawe(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__u0_inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__u0_inst0_readdata[252]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_first_bit_number = 252;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_first_bit_number = 252;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .lut_mask = "4747474700CC33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .lut_mask = "3030505F3F3F505F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .lut_mask = "0000F0F00F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[28] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92]~I .is_wysiwyg = "true";

assign \avm_local_bb1_ld__inst0_readdata[27]~input0  = avm_local_bb1_ld__inst0_readdata[27];

assign \avm_local_bb1_ld__inst0_readdata[28]~input0  = avm_local_bb1_ld__inst0_readdata[28];

assign \avm_local_bb1_ld__inst0_readdata[59]~input0  = avm_local_bb1_ld__inst0_readdata[59];

assign \avm_local_bb1_ld__inst0_readdata[60]~input0  = avm_local_bb1_ld__inst0_readdata[60];

assign \avm_local_bb1_ld__inst0_readdata[91]~input0  = avm_local_bb1_ld__inst0_readdata[91];

assign \avm_local_bb1_ld__inst0_readdata[92]~input0  = avm_local_bb1_ld__inst0_readdata[92];

assign \avm_local_bb1_ld__inst0_readdata[123]~input0  = avm_local_bb1_ld__inst0_readdata[123];

assign \avm_local_bb1_ld__inst0_readdata[124]~input0  = avm_local_bb1_ld__inst0_readdata[124];

assign \avm_local_bb1_ld__inst0_readdata[155]~input0  = avm_local_bb1_ld__inst0_readdata[155];

assign \avm_local_bb1_ld__inst0_readdata[156]~input0  = avm_local_bb1_ld__inst0_readdata[156];

assign \avm_local_bb1_ld__inst0_readdata[187]~input0  = avm_local_bb1_ld__inst0_readdata[187];

assign \avm_local_bb1_ld__inst0_readdata[188]~input0  = avm_local_bb1_ld__inst0_readdata[188];

assign \avm_local_bb1_ld__inst0_readdata[219]~input0  = avm_local_bb1_ld__inst0_readdata[219];

assign \avm_local_bb1_ld__inst0_readdata[220]~input0  = avm_local_bb1_ld__inst0_readdata[220];

assign \avm_local_bb1_ld__inst0_readdata[251]~input0  = avm_local_bb1_ld__inst0_readdata[251];

assign \avm_local_bb1_ld__inst0_readdata[252]~input0  = avm_local_bb1_ld__inst0_readdata[252];

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[27]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[27] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_first_bit_number = 27;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a27 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[28]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[28] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_first_bit_number = 28;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a28 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[59]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[59] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a59 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[60]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[60] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a60 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[91]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[91] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a91 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[92]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[92] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a92 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[123]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[123] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a123 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[124]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[124] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a124 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[155]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[155] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a155 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[156]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[156] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a156 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[187]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[187] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a187 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[188]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[188] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a188 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[219]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[219] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_first_bit_number = 219;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_first_bit_number = 219;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a219 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[220]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[220] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_first_bit_number = 220;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_first_bit_number = 220;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a220 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[251]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[251] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_first_bit_number = 251;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_first_bit_number = 251;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a251 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 (
	.portawe(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\avm_local_bb1_ld__inst0_readdatavalid~input0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|valid_rreq~1 ),
	.portadatain({\avm_local_bb1_ld__inst0_readdata[252]~input0 }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[7] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[6] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[5] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|cntr_lgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[7]~7 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[6]~6 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[5]~5 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|q_b[252] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_first_bit_number = 252;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_logical_ram_depth = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_logical_ram_width = 256;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_last_address = 255;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_first_bit_number = 252;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_address_width = 8;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|ram_block1a252 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[188] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[220] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[156] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[252] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~90_I .lut_mask = "0344CF440377CF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[92] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[60] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[28] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[124] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~91_I .lut_mask = "101CD0DC131FD3DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~90 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~91 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92_I .lut_mask = "0000FFFF0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~92 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[28] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .lut_mask = "001D331DCC1DFF1D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .lut_mask = "5533000F5533FF0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE_I .created_from = "Q(local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[155] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[219] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[187] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[251] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~93_I .lut_mask = "447744770C0C3F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[59] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[123] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[27] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[91] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~94_I .lut_mask = "0F550F550033FF33";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~93 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~94 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95_I .lut_mask = "00005555AAAAFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~95 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__u0_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[27] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~8_I .lut_mask = "50505050F550F550";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .lut_mask = "03034477CFCF4477";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .lut_mask = "0C0C44773F3F4477";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .lut_mask = "03CF03CF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[30] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[30] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[94] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[126] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~4_I .lut_mask = "207025752A7A2F7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[158] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[190] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[222] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[254] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~3_I .lut_mask = "505F3030505F3F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~5 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[30] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~8 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~11_I .lut_mask = "2B002B00FF2BFF2B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~6_I .lut_mask = "9900990000990099";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~7 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~10_I .lut_mask = "8A08EFAE0808AEAE";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~10 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~12_I .lut_mask = "8020802040104010";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~0_I .lut_mask = "4DFF004D44FF0044";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~1_I .lut_mask = "08AE08AE8AEF8AEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan1~2_I .lut_mask = "088A088AAEEFAEEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan1~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~5_I .lut_mask = "4D0C4D0CCF4DCF4D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~4 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~7 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__LessThan0~9 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~11 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~12 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__8_i~5 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9_I .lut_mask = "FF008C00FF000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[27] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~0_I .lut_mask = "C000C00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[5])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal16~1_I .lut_mask = "0800080000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .lut_mask = "0C0C11DD3F3F11DD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .lut_mask = "012389AB4567CDEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld__u0|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_reg_NO_SHIFT_REG[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__u0_NO_SHIFT_REG[31] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__u0_staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[159] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[223] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[191] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[255] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~0_I .lut_mask = "404C707C434F737F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[127] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[1]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[63] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|scfifo:rd_back_wfifo|scfifo_96b1:auto_generated|a_dpfifo_4d91:dpfifo|altsyncram_1on1:FIFOram|__ALT_INV__q_b[95] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~1_I .lut_mask = "50505F5F03F303F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__R_offset[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|__ALT_INV__ShiftRight0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2_I .lut_mask = "03030303CFCFCFCF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_ld_|lsu_bursting_read:bursting_read|lsu_bursting_pipelined_read:pipelined_read|ShiftRight0~2 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_ld__NO_SHIFT_REG[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_reg_NO_SHIFT_REG[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_ld__NO_SHIFT_REG[31] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__rstag_161to161_bb1_ld__staging_valid_NO_SHIFT_REG ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[95] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31]~I .lut_mask = "0F0F0F0FF0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_xor_i[31] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[30])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[61] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[29])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[92] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[59] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[91] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[90] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[57] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[89] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[56] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[88] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[55] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[87] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.cin(gnd),
	.sharein(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~14 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~13_I .lut_mask = "0000F0FF00000FF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~14 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~15 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~30 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~29_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~30 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~31 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~22 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~21_I .lut_mask = "00000C0C0000C3C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~22 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~23 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~18 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~17_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~18 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~19 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~26 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~25_I .lut_mask = "00000F000000F00F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~26 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~27 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~2 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~1_I .lut_mask = "00000A0A0000A5A5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~2 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~3 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~6 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~5_I .lut_mask = "000000F00000F00F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~6 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~7 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9_I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add4~9_I .lut_mask = "000000000000F00F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~25 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0_I .lut_mask = "3FFF3FFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and95_i[4]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0_I .lut_mask = "5FFF5FFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[3])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~1_I .lut_mask = "F0F0F0F000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[93] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[29]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[29])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~0_I .lut_mask = "8000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2_I .lut_mask = "FFFFFFFFF0F0F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal3~2 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6_I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7_I .lut_mask = "5555555544444444";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[14]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~21 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0_I .lut_mask = "5FFF5FFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[22]~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~24_I .lut_mask = "00AA1B1B55FF1B1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12_I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[19])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[15]~10 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13_I .lut_mask = "0F0F0F0F0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[23]~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~23_I .lut_mask = "10B010B01ABA1ABA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~29 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1_I .lut_mask = "7F7F7F7FFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[1]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~13 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0_I .lut_mask = "3F3FFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15_I .lut_mask = "00000F0F00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[17]~15 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18_I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[25]~18 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[21]~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and112_i[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~19_I .lut_mask = "227722770A0A0A0A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4_I .lut_mask = "000000000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[24]~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1_I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[16]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3_I .lut_mask = "0000FFFF0000CCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[20]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~20_I .lut_mask = "028A028A46CE46CE";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~23 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~19_I .lut_mask = "5030503F5F305F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[43] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_cmp126_not_i~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[2])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16_I .lut_mask = "0F0F0F0F0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[13]~16 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~25_I .lut_mask = "0053F0530F53FF53";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~23 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~21_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~21 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~22_I .lut_mask = "01310131CDFDCDFD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[42] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[41] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[73] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[12]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~21_I .lut_mask = "11110A5FBBBB0A5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~21 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~21 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~29_I .lut_mask = "2700270027FF27FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11_I .lut_mask = "0505050505050505";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[11]~11 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~22_I .lut_mask = "048C26AE159D37BF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~22 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~24_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~21 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~24 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~24 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~25_I .lut_mask = "00270027FF27FF27";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[72] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[40] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5_I .lut_mask = "0000000000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~3_I .lut_mask = "55330F0055330FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~4_I .lut_mask = "0F000F0000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~21 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~3 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~10_I .lut_mask = "02A202A252F252F2";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~24 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~31_I .lut_mask = "000A000AFF0AFF0A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[39] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and143_i[0]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~1_I .lut_mask = "FF00FF0000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~8_I .lut_mask = "0000000033333333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14_I .lut_mask = "000000000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[9]~14 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~7_I .lut_mask = "20702A7A25752F7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~22 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~8 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~7 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~11_I .lut_mask = "110C110CDD0CDD0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[70] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[38] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[9]~5_I .lut_mask = "00FF00FF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~2_I .lut_mask = "000000000F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0_I .lut_mask = "0505050505050505";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[8])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~0_I .lut_mask = "1111DDDD0C3F0C3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~0_I .lut_mask = "1013D0D31C1FDCDF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[69] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[37] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[8]~7_I .lut_mask = "00FF00FF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~6_I .lut_mask = "0000000033333333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9_I .lut_mask = "0000FFFF0000F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[7]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~5_I .lut_mask = "042615378CAE9DBF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~8 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~7 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~1_I .lut_mask = "0C0C44773F3F4477";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[68] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[36] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[7]~0_I .lut_mask = "00FF00FF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[10]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[10])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19_I .lut_mask = "0F0F0F0F0F000F00";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[6]~19 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~9_I .lut_mask = "1D1D00CC1D1D33FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~10_I .lut_mask = "000A000AA0AAA0AA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~9 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~2_I .lut_mask = "440344CF770377CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[67] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[35] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[6]~1_I .lut_mask = "00FF00FF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21_I .lut_mask = "00000000FFF0FFF0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[5]~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~13_I .lut_mask = "333300FF55550F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~14_I .lut_mask = "00AA00AA22222222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~13 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~4_I .lut_mask = "440C770C443F773F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[66] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[34] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[5]~3_I .lut_mask = "00FF00FF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[8]~0 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20_I .lut_mask = "00000000EEEEEEEE";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[4]~20 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~11_I .lut_mask = "11110C3FDDDD0C3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~12_I .lut_mask = "0000FF000F000F00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~11 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~3_I .lut_mask = "4700473347CC47FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[65] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[33] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[4]~2_I .lut_mask = "00FF00FF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~16_I .lut_mask = "00C000C00CCC0CCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22_I .lut_mask = "00000000FFCCFFCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[3]~22 ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~15_I .lut_mask = "220A225F770A775F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~13 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~5_I .lut_mask = "03034477CFCF4477";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[32] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[3]~4_I .lut_mask = "00FF00FF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[18]~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[18])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~17_I .lut_mask = "10B010B01ABA1ABA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datag(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26_I .extended_lut = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~26_I .lut_mask = "00550A5F0A5F2277";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~6_I .lut_mask = "01450145ABEFABEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight0~18_I .lut_mask = "0426042615371537";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~18 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~7_I .lut_mask = "028A139B46CE57DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal11~0_I .lut_mask = "A000B33300003333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[21]~17 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[23]~13 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[20]~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[22]~8 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal11~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~3_I .lut_mask = "0000000080008000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[71] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[7]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[7])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal8~0_I .lut_mask = "C0000000D5555555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[15]~10 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[13]~16 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal8~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[12]~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[14]~7 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~1_I .lut_mask = "0800080000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[5]~21 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[7]~9 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[6]~19 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[4]~20 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__15_i[3]~22 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~0_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~25 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~4_I .lut_mask = "D000D000D400D400";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~3 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_3_i[0]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2_I .lut_mask = "FFFF55FFFCFC54FC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_3_i[0]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[64] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[0]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal11~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~17 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal8~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~1_I .lut_mask = "0F003F30A0A0AFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~21 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal3~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add4~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or130_i[0]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0_I .lut_mask = "0333333353333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or130_i[0]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_reduction_3_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_or130_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~0_I .lut_mask = "FFFF000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~1_I .lut_mask = "0444047737443777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~18 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~2_I .lut_mask = "AACCAAC0A0CCA0C0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~7 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_8_i[0]~3_I .lut_mask = "FFFFCCCFFFFFDDDF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_8_i[0]~3 ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29_I .lut_mask = "0000A5A500005555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~7 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25_I .lut_mask = "0000A96500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~5 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21_I .lut_mask = "0000FFFF0000596A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[3]~4 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17_I .lut_mask = "0000FF000000569A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[4]~2 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9_I .lut_mask = "0000FF000000596A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[5]~3 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13_I .lut_mask = "0000FF000000569A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~2 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[6]~1 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5_I .lut_mask = "0000FF000000596A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[7]~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1_I .lut_mask = "0000FF000000569A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[8]~7 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65_I .lut_mask = "0000FF000000596A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~10 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[9]~5 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45_I .lut_mask = "0000FF000000569A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~31 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~106 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105_I .lut_mask = "0000FF5500000FF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~25 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~106 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89_I .lut_mask = "0000FF55000033C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~29 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~90 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~98 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97_I .lut_mask = "0000CC3C000000AA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~22 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~98 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81_I .lut_mask = "0000FF55000033C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~19 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73_I .lut_mask = "0000FF55000033C3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~73 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~9_I .lut_mask = "001D001D00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[54] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~8 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~17_I .lut_mask = "040004888C008C88";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[85] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder_I .lut_mask = "00FF00FF00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[53] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[21] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[84] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[52] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[23]~6_I .lut_mask = "00FF00FF00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~15_I .lut_mask = "0F0F00000F0FFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~15 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~16_I .lut_mask = "00FF00FF1B1B1B1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[83] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[51] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[19] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~15 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~20_I .lut_mask = "00031013A0A3B0B3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[82] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[50] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[18] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~23_I .lut_mask = "30503F50305F3F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[81] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[49] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~26_I .lut_mask = "500350F35F035FF3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~14 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~30_I .lut_mask = "00221133C0E2D1F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[80] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[48] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[16] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__14_i[19]~8_I .lut_mask = "00FF00FF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__15_i[19]~12 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~15 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1__15_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~27_I .lut_mask = "03550355CF55CF55";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~27 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~28_I .lut_mask = "00F000F00FFF0FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~27 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~32_I .lut_mask = "227722770000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[79] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[47] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[15] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~12 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~12_I .lut_mask = "02075257A2A7F2F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[78] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[46] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~20 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~13_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~16 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~13 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~18_I .lut_mask = "01450145ABEFABEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[77] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[45] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[13] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~19 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~23 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~13 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~14_I .lut_mask = "3500350035FF35FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[76] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[44] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[12] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~14 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53_I .lut_mask = "0000FF55000033C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~18 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69_I .lut_mask = "0000FF55000033C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~12 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49_I .lut_mask = "0000FF55000033C3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~32 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~110 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109_I .lut_mask = "0000FF0F00003399";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[19]~8 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~28 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~110 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93_I .lut_mask = "0000CC6C000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~30 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~94 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~102 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101_I .lut_mask = "0000CC3C000000AA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~23 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~102 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85_I .lut_mask = "0000CC3C000000AA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~20 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~86 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77_I .lut_mask = "0000CC66000000F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__14_i[23]~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~16 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57_I .lut_mask = "0000CCC6000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61_I .lut_mask = "0000FF5500003C3C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41_I .lut_mask = "0000FF55000033C3";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~41 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and143_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftRight1~8_I .lut_mask = "7777777777777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and93_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight0~4 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftRight1~8 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal16~1 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37_I .lut_mask = "000000FF00005955";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~37 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~77 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~57 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~61 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[22]~0_I .lut_mask = "8000800000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~93 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~109 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~49 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~1_I .lut_mask = "8888888800000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~101 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~85 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr1~0_I .lut_mask = "F0F0F0F000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~69 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~53 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[2]~I .lut_mask = "0002000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2]~I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[2]~I .lut_mask = "0000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2]~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[2]~I .lut_mask = "0000000000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~45 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~97 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~89 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~6_I .lut_mask = "8000000000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~105 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~6 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[9]~2_I .lut_mask = "0000000000020000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~65 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr0~1_I .lut_mask = "F000F00000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[2]~I .lut_mask = "0000000020000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[12]~0_I .lut_mask = "0002000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr0~1_I .lut_mask = "F0F0F0F000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[12]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[2]~I .lut_mask = "0000000008000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[2]~I .lut_mask = "000101170117177F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or6_i_i[15]~1_I .lut_mask = "0000000000000808";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~81 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[13]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[13])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr1~1_I .lut_mask = "AA00AA00AA00AA00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[17]~4_I .lut_mask = "0000000003030303";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[15]~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr1~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[12]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[1]~I .lut_mask = "3333D3D3FFFFDFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1]~I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[1]~I .lut_mask = "0000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[1]~I .lut_mask = "CCCCCCCC00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[1]~I .lut_mask = "3322332222222222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr1~1_I .lut_mask = "00C000C0C0C0C0C0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr1~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or6_i_i[12]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[1]~I .lut_mask = "0000000080000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~29 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~25 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr1~1_I .lut_mask = "DF5FDF5F00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[1]~I .lut_mask = "0000000000800000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[2]~I .lut_mask = "000101170117177F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[1]~I .lut_mask = "177E7EE87EE8E881";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[1]~I .lut_mask = "177E7EE87EE8E881";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|WideOr2~1_I .lut_mask = "AF00AF00AF00AF00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__WideOr2~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|sum[0]~I .lut_mask = "0000000002030003";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0]~I (
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|sum[0]~I .lut_mask = "0000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|WideOr2~1_I .lut_mask = "F000F00000FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~7_I .lut_mask = "A0A0000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~7 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[22]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr1~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[17]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or8_i_i[6]~3_I .lut_mask = "0000000001000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__WideOr2~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[6]~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|sum[0]~I .lut_mask = "444400007F0F3F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|WideOr2~1_I .lut_mask = "2F2F2F2F00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__WideOr2~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|sum[0]~I .lut_mask = "40C0000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|sum[0]~I .lut_mask = "C0C0C0C0CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|WideOr2~1_I .lut_mask = "DF55DF5500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or8_i_i[9]~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__WideOr2~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|sum[0]~I .lut_mask = "4000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[2]~I .lut_mask = "000101170117177F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|sum[0]~I .lut_mask = "6996966996696996";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[1]~I .lut_mask = "177E7EE87EE8E881";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|sum[0]~I .lut_mask = "6996966996696996";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[0] ),
	.cin(gnd),
	.sharein(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1] ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~7 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1]~I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1]~I .lut_mask = "0000000F00000FF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|__ALT_INV__sum[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~7 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~8 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2] ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~10 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2]~I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2]~I .lut_mask = "0000117700006699";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:me|__ALT_INV__sum[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~10 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~11 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3] ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~4 ),
	.shareout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3]~I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3]~I .lut_mask = "0000000F00000FF0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:hi|__ALT_INV__sum[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~4 ),
	.sharein(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|_~5 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4]~I .shared_arith = "on";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4]~I .lut_mask = "0000000000000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[4])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~DUPLICATE_I .created_from = "Q(r_data[1][0])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[3])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[2] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:c|__ALT_INV__sum[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:d|__ALT_INV__sum[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:b|__ALT_INV__sum[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:f|__ALT_INV__sum[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:e|__ALT_INV__sum[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:a|__ALT_INV__sum[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0]~I .lut_mask = "6996966996696996";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|six_three_comp:lo|sum[0] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~17_I .lut_mask = "0F0F0F0FFFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add6~0_I .lut_mask = "00FF00FFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[28] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][5] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~DUPLICATE_I .created_from = "Q(r_data[1][4])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[0][0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|r_data[1][0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33_I .lut_mask = "0000FFFF00005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add5~33 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[27] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25_I .lut_mask = "0000F0F0000011BB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29_I .lut_mask = "0000EBEB000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33_I .lut_mask = "0000FF0000001222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37_I .lut_mask = "0000EDCF000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9_I .lut_mask = "0000FF0000001222";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13_I .lut_mask = "0000ECCC000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17_I .lut_mask = "0000FF0000001333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21_I .lut_mask = "0000ECCC000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~29 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~37 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~33 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~25 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~0_I .lut_mask = "0000000001010101";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~1_I .lut_mask = "0000000100000001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1_I .lut_mask = "0000FFFF00001333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5_I .lut_mask = "0000FFFF00001333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add7~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~0_I .lut_mask = "0001000100010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_shr16_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal17~1_I .lut_mask = "0000000000010001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[94] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~0_I .lut_mask = "0000000000110011";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1_I .lut_mask = "0000000000010001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal4~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10~I .lut_mask = "3F3F3F3F3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_var__u10 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_var__u10_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_var__u10_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[14] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[6])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~16_I .lut_mask = "0000C0C03030F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[3] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[3] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[11] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|thirtysix_six_comp:local_bb1__and_i_i_popcnt_instance|ternary_add:t|o[4] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~21_I .lut_mask = "11DD11DD00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[5] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~18_I .lut_mask = "0022002288AA88AA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[12] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~19_I .lut_mask = "020202028A8A8A8A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~7_I .lut_mask = "40434C4F70737C7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~0_I .lut_mask = "AAAAAAAA00FF00FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~feeder ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[9] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[1] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~22_I .lut_mask = "00A000A050F050F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~24_I .lut_mask = "0F0F000000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[8] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~23_I .lut_mask = "00000A0AAAAA0A0A";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[10] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[2])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~20_I .lut_mask = "303000003030F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~8_I .lut_mask = "00552727AAFF2727";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~7 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5_I .lut_mask = "0522AF220577AF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~9_I .lut_mask = "0131C1F10D3DCDFD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~0_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~10_I .lut_mask = "0145236789CDABEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~9 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6_I .lut_mask = "22770A0A22775F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[16] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~17_I .lut_mask = "040404048C8C8C8C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~5_I .lut_mask = "0530F530053FF53F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~6_I .lut_mask = "1B1B00551B1BAAFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4_I .lut_mask = "270027AA275527FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~20 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~21 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~22 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~4_I .lut_mask = "101C131FD0DCD3DF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~15_I .lut_mask = "04048C8C2626AEAE";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~18 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~3_I .lut_mask = "00530F53F053FF53";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~4 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3_I .lut_mask = "220522AF770577AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[24] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[23] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[19] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~12_I .lut_mask = "03CF03CF44444444";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[18] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~14_I .lut_mask = "030003F0F300F3F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[17] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[17]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[17])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~25_I .lut_mask = "0C440C443F443F44";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~11_I .lut_mask = "550F3300550F33FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[22] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~10_I .lut_mask = "042604268CAE8CAE";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[20] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~13_I .lut_mask = "227700002277AAAA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[21])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~11_I .lut_mask = "084C084C2A6E2A6E";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~8_I .lut_mask = "00CC0C0C33FF0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~7_I .lut_mask = "050305F3F503F5F3";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~11 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~7 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8_I .lut_mask = "444477770C3F0C3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~12_I .lut_mask = "05220577AF22AF77";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~9_I .lut_mask = "082A193B4C6E5D7F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~9_I .lut_mask = "001BAA1B551BFF1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~12 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10_I .lut_mask = "1D1D00331D1DCCFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[11]~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[10]~6 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[12]~4 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[13]~3 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[20]~8 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[21]~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~0_I .lut_mask = "8000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~2_I .lut_mask = "220A225F770A775F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[26] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[25] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[25]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[25])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~7_I .lut_mask = "110511AFBB05BBAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~7 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~1_I .lut_mask = "2205770522AF77AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2_I .lut_mask = "0F5500330F55FF33";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[6] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~3_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~2_I .lut_mask = "00CC00CC00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~1_I .lut_mask = "5050505000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~0_I .lut_mask = "01510B5BA1F1ABFB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~6_I .lut_mask = "00000000C0C0C0C0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~5_I .lut_mask = "00000000C0C0C0C0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~4_I .lut_mask = "3333000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~6 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~1_I .lut_mask = "101A101AB0BAB0BA";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0_I .lut_mask = "04C434F407C737F7";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~14 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~14_I .lut_mask = "33550F0033550FFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~7 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~14 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15_I .lut_mask = "012389AB4567CDEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11_I .lut_mask = "028A139B46CE57DF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[21] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~3 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~12 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13_I .lut_mask = "030503F5F305F3F5";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~15 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~25 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~16 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~15_I .lut_mask = "0530F530053FF53F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~15 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16_I .lut_mask = "2700275527AA27FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~15 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14_I .lut_mask = "404C434F707C737F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~13 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~12 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~10 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~13_I .lut_mask = "10151A1FB0B5BABF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~14 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~13 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12_I .lut_mask = "0047CC473347FF47";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[15]~15 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[7]~11 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[17]~13 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[14]~16 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[18]~14 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[19]~12 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~1_I .lut_mask = "8000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~23 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~23_I .lut_mask = "00AA1B1B55FF1B1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~5 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~16_I .lut_mask = "012389AB4567CDEF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~23 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~16 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20_I .lut_mask = "1B001B551BAA1BFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~24_I .lut_mask = "0035F0350F35FF35";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~24 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22_I .lut_mask = "010B515BA1ABF1FB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~23 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23_I .lut_mask = "550F0033550FFF33";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~1 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~19_I .lut_mask = "00AA1B1B55FF1B1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~10 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24_I .lut_mask = "10D01CDC13D31FDF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~6 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~21_I .lut_mask = "0303505FF3F3505F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~24 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~21 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21_I .lut_mask = "50305F30503F5F3F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~5 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~11 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25_I .lut_mask = "00F00FFF35353535";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[5]~20 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[8]~22 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[9]~23 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[6]~24 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[4]~21 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[16]~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~4_I .lut_mask = "8000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft0~26_I .lut_mask = "11BB050511BBAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~8 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~7 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~9 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~22_I .lut_mask = "001D331DCC1DFF1D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~13 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~22 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~2_I .lut_mask = "F333E222D111C000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft0~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~18_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|ShiftLeft1~20_I .lut_mask = "200020A000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_add178_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[2] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~20 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[1]~2_I .lut_mask = "0300030047444744";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~18 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and184_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[1]~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~0_I .lut_mask = "CCF500F500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~20 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~19 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18_I .lut_mask = "00551B1BAAFF1B1B";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_and209_i[2]~1_I .lut_mask = "084C084C3B7F084C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~16 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~18 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17_I .lut_mask = "350035F0350F35FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and179_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~21 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19_I .lut_mask = "3300550033F055F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal20~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[2]~18 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[1]~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[0]~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~3_I .lut_mask = "1000000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[22]~2 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_shr246_i[3]~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~1 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5_I .lut_mask = "FFFFFFFFFFFFFFBF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal19~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_var__u10_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or242_i~2_I .lut_mask = "FF00FF00B300B300";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][4] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and181_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13_I .lut_mask = "0000FF0000001D1D";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17_I .lut_mask = "0000F0F000001122";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21_I .lut_mask = "0000EDDD000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__ShiftLeft1~17 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25_I .lut_mask = "0000FF0000001230";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29_I .lut_mask = "0000F9F5000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1_I .lut_mask = "0000FF000000070F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~29 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~25 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal21~0_I .lut_mask = "8080000000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[0][7] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|r_data[1][7]~DUPLICATE_I .created_from = "Q(r_data[1][7])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5_I .lut_mask = "0000FF000000070F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__and_i_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Add6~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_and17_i_0_reg_166_fifo|__ALT_INV__r_data[1][7]~DUPLICATE ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9_I .lut_mask = "0000FF000000070F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add8~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal21~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_add225_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp210_not_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i~I .lut_mask = "00D000F000F000F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~2 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__31_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or253_i~I .lut_mask = "0000000000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[0]~19 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0]~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0]~I .lut_mask = "000000000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[0] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~0_I .lut_mask = "0000000000010001";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal6~0 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal4~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29]~DUPLICATE ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1_I .lut_mask = "0000000000010001";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal6~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[86] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[22]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[22])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[74] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[10]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[10])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~3_I .lut_mask = "C000C00000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_enter_c0_eni2_NO_SHIFT_REG[75] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__8_i~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[11]~DUPLICATE_I .created_from = "Q(r_data_NO_SHIFT_REG[11])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11]~DUPLICATE ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~2_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~3 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~4_I .lut_mask = "0000000044000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~0_I .lut_mask = "8000800080008000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~1_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal2~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__9_i_0_reg_163_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5_I .lut_mask = "FFFDFFFDFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal2~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~1_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~2_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~3_I .lut_mask = "8000800080008000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~2 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~4_I .lut_mask = "0400040000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~0_I .lut_mask = "8000800000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~4 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and20_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal17~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~5_I .lut_mask = "00000000FEFFFEFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_cmp27_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_var__u4_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_lnot33_not_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1__13_i~5 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_xor_i_0_reg_164_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6_I .lut_mask = "05FF05FF37FF37FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__13_i~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1__13_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1__13_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[0] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or242_i~2 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i~I .lut_mask = "F0F0FFFFF0F0FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or257_i ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__31_i ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal20~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0_I .lut_mask = "0F0F0F0F00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|LessThan4~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal20~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_and209_i[2]~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1_I .lut_mask = "00000F0F00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Equal20~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp264_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or263_i[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_cmp266_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i~I .lut_mask = "00FF00FF00FFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1__32_i ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_reduction_9_demorgan_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_lnot279_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1__32_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_reduction_11_i~I .lut_mask = "000000000C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_reduction_11_i ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1_I .lut_mask = "0000F0F0000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_comb_bita3 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FFFFFFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "0F0FFFFF0000F0F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6_I .lut_mask = "5555555500000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\resetn~CLKENA0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\resetn~CLKENA0 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|_~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_ggb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[1]~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~2 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[2]~18 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[2] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~6 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[3]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[3] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~10 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13_I .lut_mask = "0000FFFF00005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[4]~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4]~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[4] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~14 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~17 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[5]~20 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[5] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~18 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~21 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[6]~24 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6]~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6]~I .lut_mask = "0000000000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[6] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~22 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~25 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[7]~11 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7]~I .lut_mask = "0303030303030303";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[7] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~26 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~29 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[8]~22 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8]~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[8] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[8] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~30 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~33 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[9]~23 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9]~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[9] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[9] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~34 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~37 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[10]~6 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10]~I .lut_mask = "0505050505050505";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[10] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[10] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~38 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~41 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[11]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[11] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[11] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~42 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~45 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[12]~4 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12]~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[12] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[12] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~46 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~49 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[13]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[13] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[13] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~50 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~53 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[14]~16 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14]~I .lut_mask = "0000000033333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[14] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[14] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~54 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~57 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[15]~15 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15]~I .lut_mask = "0000000033333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[15] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[15] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~58 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~61 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[16]~25 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16]~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16]~I .lut_mask = "000000000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[16] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[16] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~62 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~65 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[17]~13 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17]~I .lut_mask = "0000000055555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[17] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[17] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~66 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~69 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[18]~14 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18]~I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18]~I .lut_mask = "000000000000FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[18] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[18] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~70 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~73 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[19]~12 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19]~I .lut_mask = "0000000033333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[19] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77_I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[19] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~74 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77_I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~77 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[20]~8 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20]~I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20]~I .lut_mask = "000000000F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[20] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[20] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~78 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~81 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[21]~10 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21]~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21]~I .lut_mask = "0000000000FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[21] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[21] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~82 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~85 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_shr246_i[22]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_shr246_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1__13_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22]~I .lut_mask = "03030303FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[22] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[22] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~86 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~89 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23]~I .lut_mask = "0F5F0F5F0F5F0F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[23] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[23] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~90 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~93 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24]~I .lut_mask = "3737373737373737";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[24] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[24] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~94 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~98 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~97 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25]~I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25]~I .lut_mask = "0F0F0F0F3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[25] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[25] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~98 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~102 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101_I .lut_mask = "0000FFFF00005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~101 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26]~I .lut_mask = "3333333377777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[26] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[26] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~102 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~106 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~105 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27]~I .lut_mask = "3737373737373737";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[27] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[27] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~106 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~110 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109_I .lut_mask = "0000FFFF00005555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~109 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28]~I .lut_mask = "3333333377777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[28] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[28] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~110 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~114 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~113 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29]~I .lut_mask = "3737373737373737";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[29] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[29] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~114 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~118 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~117 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30]~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or253_i ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_or257_i ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_and230_i_0_reg_167_fifo|__ALT_INV__r_data_NO_SHIFT_REG[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30]~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30]~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30]~I .lut_mask = "3333333377777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_or263_i[30] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[30] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~118 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~122 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121_I .lut_mask = "0000FFFF00003333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~121 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_162to163_bb1__10_i_0_reg_163_fifo|r_data_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_163to164_bb1_and35_i_0_reg_164_fifo|r_data_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to165_bb1_and35_i_0_reg_165_fifo|r_data_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_164to166_bb1_cmp37_i_0_reg_166_fifo|__ALT_INV__r_data[1][0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_165to166_bb1_and35_i_0_reg_166_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__Equal19~5 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0_I .lut_mask = "00AA00AA00FF00FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_resultSign_0_i[31]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_166to167_bb1_resultSign_0_i_0_reg_167_fifo|r_data_NO_SHIFT_REG[31] ),
	.sload(vcc),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|r_data_NO_SHIFT_REG[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_167to168_bb1_or263_i_0_reg_168_fifo|__ALT_INV__r_data_NO_SHIFT_REG[31] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~122 ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125_I .lut_mask = "0000FFFF00000F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|Add9~125 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[32] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[32] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a32 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[33] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[33] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a33 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[34] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[34] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a34 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[35] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[35] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a35 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[36] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[36] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a36 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[37] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[37] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a37 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[38] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[38] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a38 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[39] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[39] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a39 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[40] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[40] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a40 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[41] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[41] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a41 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[42] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[42] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a42 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[43] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[43] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a43 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[44] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[44] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a44 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[45] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[45] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a45 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[46] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[46] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a46 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[47] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[47] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a47 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[48] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[48] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a48 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[49] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[49] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a49 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[50] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[50] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a50 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[51] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[51] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a51 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[52] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[52] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a52 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[53] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[53] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a53 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[54] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[54] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a54 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[55] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[55] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a55 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[56] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[56] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a56 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[57] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[57] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a57 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[58] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[58] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a58 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[59] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[59] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a59 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[60] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[60] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a60 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[61] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[61] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a61 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[62] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[62] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a62 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|valid_wreq ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|pulse_ram_output~0 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|reg_data_in[63] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|cntr_hgb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[63] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_logical_ram_depth = 16;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_logical_ram_width = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_last_address = 15;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_address_width = 4;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|ram_block1a63 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[32] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0_I .lut_mask = "0808080808080808";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[4] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_1to172_bb1_arrayidx5_RM_0_reg_172_fifo|acl_fifo:fifo|scfifo:scfifo_component|scfifo_s6d1:auto_generated|a_dpfifo_m9a1:dpfifo|altsyncram_rkn1:FIFOram|q_b[4] ),
	.clrn(\resetn~CLKENA0 ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE_I .created_from = "Q(data[0][4])";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][4]~DUPLICATE ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|r_data[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|__ALT_INV__r_data[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28_I .lut_mask = "0000AAAA5555FFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_data_fifo:rnode_172to173_bb1_arrayidx5_RM_0_reg_173_fifo|acl_staging_reg:staging_reg|o_data[4]~28 ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|always1~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~0_I .lut_mask = "AAAA000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__thread_counter[7] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__match_next_page~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_common_burst~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~1_I .lut_mask = "0000000000020002";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|o_new_page~I .lut_mask = "FF7FFF33FF77FF33";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0_I .lut_mask = "00000F0FFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~I .lut_mask = "00000000000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|__ALT_INV__counter_reg_bit[4] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita3~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_comb_bita4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0_I .lut_mask = "FFFF0000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|rd_ptr_lsb~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[0] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0_I .lut_mask = "5050FAFA7070F8F8";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.cin(gnd),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~I .lut_mask = "00000000000000FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__rd_ptr_lsb ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5_I .lut_mask = "0000CCCC00CCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[1] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1_I .lut_mask = "00A800A857FF57FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita0~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2_I .lut_mask = "00A800A857FF57FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita1~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ),
	.cout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3_I .lut_mask = "05AF05AF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I (
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.cin(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita2~COUT ),
	.sumout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3~I .lut_mask = "0000FFFF000000FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_comb_bita3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|_~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|counter_reg_bit[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|low_addressa[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~1 ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__pulse_ram_output~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_hgb:rd_ptr_msb|__ALT_INV__counter_reg_bit[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|__ALT_INV__low_addressa[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4_I .lut_mask = "05AF05AF078F078F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[33] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[34] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[2]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[35] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[35] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[3]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[36] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[36] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[36] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[36] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[37] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[37]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[37] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[37] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[37] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[5]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[38] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[38] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[38] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[38] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[39] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7_I .lut_mask = "00000000C0C0C0C0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[40] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[40] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[40] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[40] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[8] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8_I .lut_mask = "0C0C0C0C00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[41] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[41] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[41] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[41] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~9 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[42] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[42] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[42] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[42] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[43] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[43] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11_I .lut_mask = "00000000A0A0A0A0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~11 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[44] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[44] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[44] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[44] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[12]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12_I .lut_mask = "0808080808080808";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~12 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[45] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[45] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[45] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13_I .lut_mask = "00000000A0A0A0A0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[46] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[46]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[46] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[46] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[46] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[14]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14_I .lut_mask = "0C0C0C0C00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[47] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[47] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[47] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[47] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[15]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15_I .lut_mask = "0808080808080808";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[48] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[48]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[48] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[48] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[48] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[49] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[49] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[49] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[49] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[17]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17_I .lut_mask = "0088008800880088";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~17 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[50] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[50] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[50] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[50] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[18]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[51] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[51] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[51] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[51] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[19]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~19 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[52] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[52]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[52] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[52] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[52] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[20]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~20 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[53] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[53] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[21]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[54] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[54] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[54] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[54] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[22]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[55] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[55] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[55] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|__ALT_INV__local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[55] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[23]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23_I .lut_mask = "0088008800880088";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~23 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[56] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[56] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder_I .lut_mask = "3333333333333333";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[56] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[56] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~24 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[57] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[57] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[57] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[57] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[25]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~25 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[58] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[58] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[58] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26_I .lut_mask = "0C0C0C0C00000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~26 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[59] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[59]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[59] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[59] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[59] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27_I .lut_mask = "0000000088888888";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[60] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[60] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~28 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[61] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[61]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[61] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder_I .lut_mask = "5555555555555555";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[61] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[61] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29_I .lut_mask = "5555000000000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~29 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[62] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[62] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~30 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|__ALT_INV__q_b[63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~feeder ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|r_data[63]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_data[63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder_I .lut_mask = "0F0F0F0F0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~feeder ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_fifo:fifo|scfifo:scfifo_component|scfifo_55d1:auto_generated|a_dpfifo_v7a1:dpfifo|altsyncram_7hn1:FIFOram|q_b[63] ),
	.sload(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|acl_stall_free_sink:local_bb1_c0_exit_c0_exi1_instance|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_output_regs_ready ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|local_bb1_c0_exit_c0_exi1_NO_SHIFT_REG[63] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|o_stall ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[31] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31_I .lut_mask = "5050505000000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22]~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32_I .lut_mask = "00000000FFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~1_I .lut_mask = "00000000A0A0A0A0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1_I .lut_mask = "0F0F0F0F3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~33 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34_I .lut_mask = "00CC00CC00CC00CC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~34 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~36 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~37 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~38 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~39 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[0] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[32] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_first_bit_number = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a32 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[1] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[33] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_first_bit_number = 33;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a33 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[2] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[34] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_first_bit_number = 34;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a34 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[3] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[35] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_first_bit_number = 35;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a35 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[4] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[36] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_first_bit_number = 36;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a36 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[5] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[37] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_first_bit_number = 37;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a37 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[6] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[38] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_first_bit_number = 38;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a38 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[7] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[39] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_first_bit_number = 39;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a39 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[8] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[40] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_first_bit_number = 40;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a40 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[9] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[41] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_first_bit_number = 41;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a41 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[10] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[42] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_first_bit_number = 42;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a42 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[11] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[43] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_first_bit_number = 43;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a43 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[12] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[44] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_first_bit_number = 44;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a44 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[13] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[45] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_first_bit_number = 45;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a45 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[14] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[46] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_first_bit_number = 46;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a46 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[15] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[47] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_first_bit_number = 47;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a47 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[16] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[48] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_first_bit_number = 48;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a48 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[17] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[49] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_first_bit_number = 49;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a49 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[18] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[50] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_first_bit_number = 50;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a50 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[19] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[51] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_first_bit_number = 51;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a51 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[20] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[52] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_first_bit_number = 52;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a52 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[21] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[53] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_first_bit_number = 53;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a53 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[22] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[54] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_first_bit_number = 54;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a54 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[23] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[55] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_first_bit_number = 55;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a55 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[24] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[56] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_first_bit_number = 56;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a56 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[25] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[57] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_first_bit_number = 57;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a57 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[26] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[58] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_first_bit_number = 58;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a58 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[27] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[59] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_first_bit_number = 59;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a59 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[28] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[60] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_first_bit_number = 60;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a60 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[29] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[61] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_first_bit_number = 61;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a61 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[30] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[62] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_first_bit_number = 62;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a62 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[31] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[63] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_first_bit_number = 63;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a63 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[32] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[64] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_first_bit_number = 64;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a64 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[33] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[65] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_first_bit_number = 65;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a65 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[34] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[66] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_first_bit_number = 66;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a66 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[35] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[67] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_first_bit_number = 67;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a67 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[36] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[68] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_first_bit_number = 68;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a68 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[69] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_first_bit_number = 69;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a69 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[38] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[70] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_first_bit_number = 70;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a70 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[39] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[71] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_first_bit_number = 71;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a71 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1_I .lut_mask = "F0F0F0F000F000F0";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[1]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0_I .lut_mask = "FFFFFFFFF0FFF0FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|wptr[0]~DUPLICATE_I .created_from = "Q(wptr[0])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr[0]~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__wptr_copy[0] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|__ALT_INV__write~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0_I .lut_mask = "30303030BABABABA";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][32] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[32]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][32] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[32] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[32]~0_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][33] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[33]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][33] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[33] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[33]~1_I .lut_mask = "0A5F0A5F0A5F0A5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][34] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[34]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[34] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][34] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[34]~2_I .lut_mask = "11BB11BB11BB11BB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][35] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[35]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[35] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][35] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[35]~3_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[36] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][36] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[36]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[36] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][36] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[36]~4_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[37] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][37] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[37]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][37] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[37] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[37]~5_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[38] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][38] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[38]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][38] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[38] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[38]~6_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][39] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[39]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[39] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][39] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[39]~7_I .lut_mask = "11BB11BB11BB11BB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[40] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][40] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][40] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[40] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[40]~8_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[41] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][41] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[41] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][41] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[41]~9_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[42] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][42] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][42] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[42] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[42]~10_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][43] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][43] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[43] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[43]~11_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[44] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][44] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][44] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[44] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[44]~12_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][45] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][45] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[45] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[45]~13_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[46] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][46] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[46]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[46] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][46] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[46]~14_I .lut_mask = "11BB11BB11BB11BB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[47] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][47] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[47] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][47] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[47]~15_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[48] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][48] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[48]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][48] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[48] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[48]~16_I .lut_mask = "2727272727272727";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[49] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][49] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[49] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][49] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[49]~17_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[50] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][50] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[50] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][50] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[50]~18_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[51] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][51] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[51] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][51] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[51]~19_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[52] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][52] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[52]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][52] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[52] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[52]~20_I .lut_mask = "0A0A0A0A5F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][53] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[53] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][53] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[53]~21_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[54] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][54] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[54] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][54] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[54]~22_I .lut_mask = "00550055AAFFAAFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[55] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][55] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][55] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[55] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[55]~23_I .lut_mask = "00F000F00FFF0FFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[56] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][56] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[56] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][56] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[56]~24_I .lut_mask = "00FF00FF55555555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[57] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][57] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][57] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[57] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[57]~25_I .lut_mask = "0A0A0A0A5F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][58] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[58] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][58] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[58]~26_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[59] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][59] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[59]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][59] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[59] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[59]~27_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][60] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][60] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[60] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[60]~28_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[61] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][61] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[61]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[61] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][61] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[61]~29_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][62] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][62] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[62] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[62]~30_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][63] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[63]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[63] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][63] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[63]~31_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[64] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][64] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[64]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][64] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[64] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[64]~32_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[65] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][65] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[65]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][65] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[65] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[65]~33_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[66] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][66] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[66]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][66] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[66] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[66]~34_I .lut_mask = "2727272727272727";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[67] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][67] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[67]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[67] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][67] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[67]~35_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[68] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][68] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[68]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[68] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][68] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[68]~36_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[69] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][69] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[69]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][69] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[69] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[69]~37_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[70] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][70] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[70]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][70] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[70] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[70]~38_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[71] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][71] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[71]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[71] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][71] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[71]~39_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~40 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41_I .lut_mask = "00CC00CC00CC00CC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~42 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~46 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47_I .lut_mask = "00CC00CC00CC00CC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~47 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~48 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~49 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~50 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52_I .lut_mask = "00000000FFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~52 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53_I .lut_mask = "00000000FFFF0000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~56 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57_I .lut_mask = "00CC00CC00CC00CC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~57 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~58 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60_I .lut_mask = "00CC00CC00CC00CC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~60 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~61 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62_I .lut_mask = "5555000055550000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~62 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~63 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[37]~1 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[0] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~64 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder_I .lut_mask = "00000000FFFFFFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~2_I .lut_mask = "00000000CC00CC00";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~2 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2_I .lut_mask = "0000FFFF0F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~65 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66_I .lut_mask = "0C0C0C0C0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~67 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~68 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69_I .lut_mask = "00CC00CC00CC00CC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[6] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[7] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71_I .lut_mask = "0C0C0C0C0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[8] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~72_I .lut_mask = "00CC00CC00CC00CC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~72 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[9] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~73 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[10] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~74_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~74 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[11] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~75_I .lut_mask = "0000F0F00000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~75 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~76_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~76 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[13] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~77_I .lut_mask = "00000000FFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~77 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~78_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~78 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79_I .lut_mask = "0000FFFF00000000";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~79 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[40] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[72] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_first_bit_number = 72;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a72 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[41] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[73] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_first_bit_number = 73;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a73 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[42] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[74] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_first_bit_number = 74;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a74 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[43] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[75] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_first_bit_number = 75;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a75 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[44] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[76] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_first_bit_number = 76;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a76 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[45] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[77] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_first_bit_number = 77;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a77 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[46] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[78] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_first_bit_number = 78;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a78 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[47] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[79] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_first_bit_number = 79;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a79 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[48] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[80] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_first_bit_number = 80;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a80 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[49] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[81] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_first_bit_number = 81;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a81 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[50] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[82] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_first_bit_number = 82;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a82 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[51] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[83] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_first_bit_number = 83;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a83 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[52] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[84] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_first_bit_number = 84;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a84 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[53] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[85] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_first_bit_number = 85;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a85 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[54] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[86] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_first_bit_number = 86;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a86 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[55] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[87] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_first_bit_number = 87;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a87 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[56] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[88] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_first_bit_number = 88;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a88 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[57] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[89] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_first_bit_number = 89;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a89 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[58] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[90] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_first_bit_number = 90;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a90 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[59] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[91] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_first_bit_number = 91;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a91 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[60] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[92] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_first_bit_number = 92;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a92 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[61] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[93] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_first_bit_number = 93;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a93 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[62] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[94] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_first_bit_number = 94;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a94 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[63] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[95] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_first_bit_number = 95;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a95 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[64] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[96] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_first_bit_number = 96;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a96 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[65] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[97] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_first_bit_number = 97;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a97 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[66] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[98] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_first_bit_number = 98;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a98 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[67] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[99] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_first_bit_number = 99;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a99 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[68] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[100] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_first_bit_number = 100;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a100 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[69] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[101] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_first_bit_number = 101;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a101 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[70] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[102] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_first_bit_number = 102;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a102 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[71] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[103] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_first_bit_number = 103;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a103 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[72] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[104] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_first_bit_number = 104;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a104 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[73] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[105] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_first_bit_number = 105;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a105 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[74] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[106] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_first_bit_number = 106;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a106 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[75] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[107] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_first_bit_number = 107;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a107 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[76] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[108] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_first_bit_number = 108;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a108 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[77] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[109] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_first_bit_number = 109;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a109 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[78] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[110] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_first_bit_number = 110;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a110 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[79] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[111] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_first_bit_number = 111;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a111 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[72] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][72] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[72]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[72] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][72] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[72]~40_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[73] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][73] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[73]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[73] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][73] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[73]~41_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[74] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][74] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[74]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][74] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[74] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[74]~42_I .lut_mask = "0A0A0A0A5F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[75] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][75] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[75]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][75] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[75] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[75]~43_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[76] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][76] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[76]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[76] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][76] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[76]~44_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[77] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][77] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[77]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][77] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[77] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[77]~45_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[78] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][78] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[78]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[78] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][78] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[78]~46_I .lut_mask = "11111111BBBBBBBB";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[79] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][79] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[79]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[79] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][79] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[79]~47_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[80] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][80] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[80] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][80] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[80]~48_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[81] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][81] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][81] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[81] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[81]~49_I .lut_mask = "0A0A0A0A5F5F5F5F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[82] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][82] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[82]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[82] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][82] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[82]~50_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[83] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[83]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][83]~DUPLICATE_I .created_from = "Q(data[0][83])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[83] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][83]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[83]~51_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[84] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][84] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[84]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][84] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[84] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[84]~52_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[85] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][85] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[85]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[85] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][85] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[85]~53_I .lut_mask = "03CF03CF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[86] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][86] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[86]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[86] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][86] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[86]~54_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[87] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][87] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[87]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[87] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][87] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[87]~55_I .lut_mask = "11DD11DD11DD11DD";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[88] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][88] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[88] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][88] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[88]~56_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[89] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][89] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[89]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][89] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[89] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[89]~57_I .lut_mask = "2222222277777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[90] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][90] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[90]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[90] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][90] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[90]~58_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[91] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][91] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[91]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[91] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][91] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[91]~59_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[92] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][92] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[92]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][92] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[92] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[92]~60_I .lut_mask = "2222222277777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[93] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][93] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[93]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[93] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][93] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[93]~61_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[94] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][94] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[94] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][94] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[94]~62_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[95] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][95] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[95]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][95] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[95] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[95]~63_I .lut_mask = "2222222277777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[96] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][96] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[96]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[96] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][96] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[96]~64_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[97] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][97] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[97]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[97] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][97] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[97]~65_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[98] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][98] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[98]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[98] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][98] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[98]~66_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[99] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][99] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[99]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[99] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][99] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[99]~67_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[100] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][100] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[100]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][100] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[100] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[100]~68_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[101] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][101] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[101]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][101] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[101] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[101]~69_I .lut_mask = "0A5F0A5F0A5F0A5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[102] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][102] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[102]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[102] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][102] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[102]~70_I .lut_mask = "00550055AAFFAAFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[103] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][103] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[103]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[103] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][103] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[103]~71_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[104] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][104] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[104]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][104] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[104] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[104]~72_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[105] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][105] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[105]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[105] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][105] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[105]~73_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[106] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][106] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[106]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][106] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[106] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[106]~74_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[107] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][107] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[107]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][107] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[107] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[107]~75_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[108] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][108] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[108]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][108] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[108] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[108]~76_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[109] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][109] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[109]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[109] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][109] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[109]~77_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[110] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][110] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[110]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][110] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[110] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[110]~78_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[111] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][111] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[111]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][111] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[111] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[111]~79_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[16] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~80_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~80 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~81_I .lut_mask = "00000000FFFF0000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~81 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~82_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~82 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~83_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~83 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~84_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~84 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~85_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~85 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~86_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~86 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~87 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[24] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~88_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~88 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89_I .lut_mask = "0C0C0C0C0C0C0C0C";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~89 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~90 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~91 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[28] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~92_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~92 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93_I .lut_mask = "00000000CCCCCCCC";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~93 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~94_I .lut_mask = "0C0C0C0C0C0C0C0C";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~94 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[31] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~95_I .lut_mask = "00000000CCCCCCCC";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft0~95 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84]~2 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~3_I .lut_mask = "000000000A0A0A0A";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~3 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3_I .lut_mask = "0000FFFF0F0FFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[0] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[1] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[3] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[4] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[5] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[6] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[7] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[8] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[9] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[10] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[11] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[12] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[13] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[14] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[15] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[16] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[17] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[18] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[19] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[20] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[21] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[22] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[23] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[80] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[112] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_first_bit_number = 112;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a112 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[81] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[113] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_first_bit_number = 113;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a113 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[82] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[114] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_first_bit_number = 114;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a114 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[83] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[115] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_first_bit_number = 115;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a115 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[84] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[116] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_first_bit_number = 116;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a116 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[85] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[117] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_first_bit_number = 117;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a117 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[86] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[118] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_first_bit_number = 118;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a118 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[87] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[119] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_first_bit_number = 119;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a119 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[88] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[120] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_first_bit_number = 120;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a120 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[89] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[121] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_first_bit_number = 121;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a121 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[90] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[122] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_first_bit_number = 122;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a122 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[91] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[123] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_first_bit_number = 123;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a123 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[92] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[124] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_first_bit_number = 124;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a124 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[93] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[125] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_first_bit_number = 125;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a125 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[94] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[126] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_first_bit_number = 126;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a126 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[95] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[127] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_first_bit_number = 127;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a127 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[96] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[128] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_first_bit_number = 128;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a128 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[97] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[129] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_first_bit_number = 129;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a129 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[98] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[130] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_first_bit_number = 130;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a130 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[99] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[131] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_first_bit_number = 131;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a131 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[100] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[132] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_first_bit_number = 132;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a132 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[101] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[133] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_first_bit_number = 133;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a133 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[102] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[134] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_first_bit_number = 134;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a134 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[103] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[135] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_first_bit_number = 135;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a135 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[104] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[136] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_first_bit_number = 136;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a136 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[105] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[137] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_first_bit_number = 137;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a137 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[106] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[138] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_first_bit_number = 138;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a138 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[107] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[139] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_first_bit_number = 139;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a139 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[108] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[140] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_first_bit_number = 140;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a140 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[109] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[141] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_first_bit_number = 141;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a141 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[110] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[142] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_first_bit_number = 142;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a142 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[111] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[143] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_first_bit_number = 143;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a143 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[112] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[144] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_first_bit_number = 144;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a144 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[113] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[145] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_first_bit_number = 145;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a145 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[114] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[146] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_first_bit_number = 146;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a146 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[115] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[147] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_first_bit_number = 147;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a147 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[148] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_first_bit_number = 148;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a148 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[117] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[149] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_first_bit_number = 149;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a149 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[118] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[150] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_first_bit_number = 150;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a150 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[119] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[151] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_first_bit_number = 151;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a151 .clk1_output_clock_enable = "ena1";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[112] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][112] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[112]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[112] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][112] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[112]~80_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[113] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][113] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[113]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[113] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][113] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[113]~81_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[114] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][114] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[114]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][114] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[114] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[114]~82_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[115] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][115] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[115]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][115] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[115] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[115]~83_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[116] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][116] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[116]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[116] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][116] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[116]~84_I .lut_mask = "11111111BBBBBBBB";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[117] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][117] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[117]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[117] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][117] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[117]~85_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[118] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][118] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[118]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[118] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][118] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[118]~86_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[119] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][119] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[119]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[119] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][119] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[119]~87_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[120] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][120] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[120]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[120] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][120] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[120]~88_I .lut_mask = "00550055AAFFAAFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[121] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[121]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE_I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE_I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE_I .is_wysiwyg = "true";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][121]~DUPLICATE_I .created_from = "Q(data[0][121])";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[121] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][121]~DUPLICATE ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[121]~89_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[122] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][122] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[122]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][122] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[122] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[122]~90_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[123] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][123] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[123]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][123] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[123] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[123]~91_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[124] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][124] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[124]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][124] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[124] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[124]~92_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[125] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][125] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[125]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[125] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][125] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[125]~93_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[126] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][126] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[126]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][126] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[126] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[126]~94_I .lut_mask = "2222222277777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[127] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][127] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[127]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][127] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[127] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[127]~95_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[128] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][128] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[128]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][128] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[128] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[128]~96_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[129] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][129] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[129]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][129] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[129] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[129]~97_I .lut_mask = "2727272727272727";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[130] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][130] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[130]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][130] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[130] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[130]~98_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[131] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][131] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[131]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[131] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][131] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[131]~99_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[132] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][132] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[132]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[132] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][132] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[132]~100_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[133] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][133] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[133]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][133] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[133] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[133]~101_I .lut_mask = "0C0C0C0C3F3F3F3F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[134] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][134] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[134]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[134] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][134] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[134]~102_I .lut_mask = "03030303CFCFCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[135] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][135] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[135]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[135] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][135] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[135]~103_I .lut_mask = "03030303CFCFCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[136] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][136] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[136]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[136] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][136] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[136]~104_I .lut_mask = "03CF03CF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[137] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][137] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[137]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[137] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][137] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[137]~105_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[138] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][138] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[138]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[138] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][138] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[138]~106_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[139] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][139] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[139]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][139] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[139] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[139]~107_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[140] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][140] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[140]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[140] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][140] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[140]~108_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[141] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][141] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[141]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[141] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][141] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[141]~109_I .lut_mask = "03CF03CF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[142] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][142] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[142]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[142] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][142] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[142]~110_I .lut_mask = "03CF03CF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[143] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][143] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[143]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[143] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][143] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[143]~111_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[144] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][144] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[144]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[144] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][144] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[144]~112_I .lut_mask = "03CF03CF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[145] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][145] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[145]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[145] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][145] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[145]~113_I .lut_mask = "05050505AFAFAFAF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[146] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][146] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[146]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][146] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[146] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[146]~114_I .lut_mask = "4444444477777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[147] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][147] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[147]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][147] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[147] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[147]~115_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[148] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][148] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[148]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[148] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][148] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[148]~116_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[149] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][149] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[149]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[149] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][149] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[149]~117_I .lut_mask = "03CF03CF03CF03CF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[150] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][150] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[150]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][150] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[150] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[150]~118_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[151] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][151] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[151]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][151] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[151] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[151]~119_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[24] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[25] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[26] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[27] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[28] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[29] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_writedata[30] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_writedata[31] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sclr(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|reg_lsu_i_address[4] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[116]~3 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~4_I .lut_mask = "0000000088888888";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~4 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~4_I .lut_mask = "0033003300330033";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[159]~4 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5_I .lut_mask = "AEEEFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~0 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~1 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~2 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~3 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~4 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~5 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~6 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~7 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~8 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~9 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~10 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~11 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~12 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~13 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~14 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~15 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~16 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~17 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~18 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~19 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~20 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~21 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~22 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~23 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~24 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~25 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~26 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~27 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~28 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~29 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~30 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~31 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~5 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[120] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[152] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_first_bit_number = 152;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a152 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[121] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[153] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_first_bit_number = 153;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a153 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[122] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[154] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_first_bit_number = 154;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a154 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[123] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[155] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_first_bit_number = 155;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a155 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[124] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[156] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_first_bit_number = 156;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a156 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[125] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[157] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_first_bit_number = 157;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a157 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[126] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[158] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_first_bit_number = 158;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a158 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[127] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[159] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_first_bit_number = 159;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a159 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[128] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[160] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_first_bit_number = 160;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a160 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[129] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[161] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_first_bit_number = 161;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a161 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[130] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[162] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_first_bit_number = 162;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a162 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[131] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[163] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_first_bit_number = 163;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a163 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[132] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[164] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_first_bit_number = 164;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a164 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[133] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[165] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_first_bit_number = 165;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a165 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[134] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[166] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_first_bit_number = 166;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a166 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[135] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[167] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_first_bit_number = 167;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a167 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[136] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[168] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_first_bit_number = 168;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a168 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[137] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[169] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_first_bit_number = 169;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a169 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[138] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[170] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_first_bit_number = 170;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a170 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[139] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[171] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_first_bit_number = 171;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a171 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[140] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[172] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_first_bit_number = 172;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a172 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[141] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[173] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_first_bit_number = 173;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a173 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[142] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[174] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_first_bit_number = 174;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a174 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[143] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[175] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_first_bit_number = 175;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a175 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[144] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[176] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_first_bit_number = 176;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a176 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[145] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[177] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_first_bit_number = 177;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a177 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[146] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[178] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_first_bit_number = 178;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a178 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[147] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[179] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_first_bit_number = 179;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a179 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[148] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[180] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_first_bit_number = 180;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a180 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[149] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[181] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_first_bit_number = 181;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a181 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[150] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[182] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_first_bit_number = 182;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a182 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[151] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[183] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_first_bit_number = 183;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a183 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[152] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[184] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_first_bit_number = 184;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a184 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[153] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[185] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_first_bit_number = 185;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a185 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[154] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[186] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_first_bit_number = 186;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a186 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[155] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[187] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_first_bit_number = 187;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a187 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[156] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[188] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_first_bit_number = 188;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a188 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[157] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[189] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_first_bit_number = 189;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a189 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[158] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[190] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_first_bit_number = 190;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a190 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[159] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[191] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_first_bit_number = 191;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a191 .clk1_output_clock_enable = "ena1";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[152] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][152] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[152]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][152] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[152] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[152]~120_I .lut_mask = "330F330F330F330F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[153] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][153] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[153]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][153] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[153] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[153]~121_I .lut_mask = "550F550F550F550F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[154] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][154] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[154]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][154] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[154] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[154]~122_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[155] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][155] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[155]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[155] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][155] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[155]~123_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[156] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][156] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[156]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[156] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][156] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[156]~124_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[157] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][157] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[157]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][157] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[157] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[157]~125_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[158] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][158] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[158]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][158] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[158] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[158]~126_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[159] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][159] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[159]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[159] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][159] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[159]~127_I .lut_mask = "00FF00FF0F0F0F0F";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[160] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][160] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[160]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[160] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][160] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[160]~128_I .lut_mask = "00FF00FF55555555";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[161] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][161] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[161]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[161] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][161] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[161]~129_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[162] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][162] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[162]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[162] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][162] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[162]~130_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[163] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][163] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[163]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[163] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][163] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[163]~131_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[164] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][164] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[164]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][164] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[164] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[164]~132_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[165] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][165] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[165]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][165] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[165] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[165]~133_I .lut_mask = "0A0A0A0A5F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[166] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][166] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[166]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][166] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[166] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[166]~134_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[167] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][167] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[167]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[167] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][167] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[167]~135_I .lut_mask = "05AF05AF05AF05AF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[168] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][168] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[168]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[168] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][168] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[168]~136_I .lut_mask = "05050505AFAFAFAF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[169] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][169] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[169]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[169] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][169] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[169]~137_I .lut_mask = "03CF03CF03CF03CF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[170] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][170] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[170]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][170] ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[170] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[170]~138_I .lut_mask = "2727272727272727";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[171] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][171] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[171]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][171] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[171] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[171]~139_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[172] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][172] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[172]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][172] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[172] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[172]~140_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[173] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][173] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[173]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][173] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[173] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[173]~141_I .lut_mask = "2222222277777777";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[174] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][174] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[174]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][174] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[174] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[174]~142_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[175] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][175] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[175]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][175] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[175] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[175]~143_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[176] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][176] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[176]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][176] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[176] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[176]~144_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[177] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][177] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[177]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][177] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[177] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[177]~145_I .lut_mask = "0A0A0A0A5F5F5F5F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[178] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][178] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[178]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[178] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][178] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[178]~146_I .lut_mask = "00FF00FF0F0F0F0F";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[179] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][179] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[179]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][179] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[179] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[179]~147_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[180] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][180] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[180]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][180] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[180] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[180]~148_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[181] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][181] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[181]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[181] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][181] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[181]~149_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[182] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][182] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[182]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][182] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[182] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[182]~150_I .lut_mask = "2222222277777777";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[183] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][183] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[183]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[183] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][183] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[183]~151_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[184] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][184] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[184]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][184] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[184] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[184]~152_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[185] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][185] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[185]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[185] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][185] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[185]~153_I .lut_mask = "03030303CFCFCFCF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[186] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][186] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[186]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[186] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][186] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[186]~154_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[187] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][187] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[187]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][187] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[187] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[187]~155_I .lut_mask = "00AA00AA55FF55FF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[188] ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][188] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[188]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[188] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][188] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[188]~156_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[189] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][189] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[189]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][189] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[189] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[189]~157_I .lut_mask = "00AA00AA55FF55FF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[190] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][190] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[190]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[190] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][190] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[190]~158_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder_I (
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|__ALT_INV__q_b[191] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder_I .lut_mask = "00000000FFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~feeder ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data_hold~0 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191]~I (
	.clk(\clock~CLKENA0 ),
	.asdata(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|data[0][191] ),
	.sload(vcc),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|r_data[191]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_valid ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|__ALT_INV__r_data[191] ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_data_fifo:fifo|acl_ll_fifo:fifo|__ALT_INV__data[0][191] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_data_fifo:fifo_outer|acl_staging_reg:staging_reg|o_data[191]~159_I .lut_mask = "05AF05AF05AF05AF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5_I (
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~5_I .lut_mask = "000000000000F0F0";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6_I (
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~5 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~6_I .lut_mask = "0000000033333333";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[176]~6 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7_I .lut_mask = "AEEEFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~32 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~33 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~34 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~35 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~36 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~37 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~38 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~39 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~40 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~41 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~42 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~43 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~44 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[173]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~45 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[173] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[173]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[173]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[174]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~46 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[174] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[174]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[174]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[175]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~47 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[175] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[175]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[175]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~48 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[177]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~49 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[177] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[177]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[177]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[178]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~50 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[178] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[178]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[178]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[179]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~51 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[179] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[179]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[179]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[180]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~52 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[180] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[180]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[180]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[181]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~53 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[181] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[181]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[181]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[182]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~54 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[182] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[182]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[182]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[183]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~55 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[183] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[183]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[183]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[184]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~56 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[184] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[184]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[184]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[185]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~57 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[185] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[185]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[185]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[186]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~58 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[186] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[186]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[186]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[187]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~59 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[187] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[187]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[187]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[188]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~60 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[188] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[188]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[188]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[189]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~61 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[189] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[189]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[189]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[190]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~62 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[190] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[190]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[190]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[191]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~63 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[176]~7 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[191] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[191]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[191]~I .is_wysiwyg = "true";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[3] ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[4] ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|__ALT_INV__reg_lsu_i_address[2] ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft1~6_I .lut_mask = "0000555500000000";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8_I (
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__ShiftLeft1~6 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__comb~0 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~8_I .lut_mask = "000000000000FFFF";

cyclonev_lcell_comb \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9_I (
	.dataa(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__valid~DUPLICATE ),
	.datab(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__w_fifo_full ),
	.datac(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__waiting~3 ),
	.datad(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__timeout_counter[4]~DUPLICATE ),
	.datae(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|bursting_coalescer:coalescer|__ALT_INV__o_new_page~1 ),
	.dataf(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|__ALT_INV__wm_writedata[208]~8 ),
	.combout(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9_I .shared_arith = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9_I .extended_lut = "off";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9_I .lut_mask = "AEEEFFFFFFFFFFFF";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[192]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~64 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[192] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[192]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[192]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[193]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~65 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[193] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[193]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[193]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[194]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~66 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[194] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[194]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[194]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[195]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~67 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[195] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[195]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[195]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[196]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~68 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[196] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[196]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[196]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[197]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~69 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[197] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[197]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[197]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[198]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~70 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[198] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[198]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[198]~I .is_wysiwyg = "true";

dffeas \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[199]~I (
	.clk(\clock~CLKENA0 ),
	.d(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|ShiftLeft0~71 ),
	.clrn(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|sync_rstn_MS[1] ),
	.ena(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[208]~9 ),
	.q(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[199] ));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[199]~I .power_up = "low";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[199]~I .is_wysiwyg = "true";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[160] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[192] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_first_bit_number = 192;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a192 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[161] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[193] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_first_bit_number = 193;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a193 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[162] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[194] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_first_bit_number = 194;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a194 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[163] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[195] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_first_bit_number = 195;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a195 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[164] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[196] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_first_bit_number = 196;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a196 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[165] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[197] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_first_bit_number = 197;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a197 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[166] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[198] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_first_bit_number = 198;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a198 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[167] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[199] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_first_bit_number = 199;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a199 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[168] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[200] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_first_bit_number = 200;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a200 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[169] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[201] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_first_bit_number = 201;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a201 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[170] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[202] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_first_bit_number = 202;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a202 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[171] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[203] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_a_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_address_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_read_enable_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_data_out_clock = "clock1";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_first_bit_number = 203;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_data_width = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_address_width = 5;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .port_b_read_during_write_mode = "new_data_no_nbe_read";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .clk0_core_clock_enable = "ena0";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a203 .clk1_output_clock_enable = "ena1";

cyclonev_ram_block \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 (
	.portawe(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.portbre(vcc),
	.clk0(\clock~CLKENA0 ),
	.clk1(\clock~CLKENA0 ),
	.ena0(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wr_page~0 ),
	.ena1(\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|pulse_ram_output~2 ),
	.portadatain({\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|wm_writedata[172] }),
	.portaaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[4] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[3] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[2] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[1] ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|cntr_igb:wr_ptr|counter_reg_bit[0] }),
	.portbaddr({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[4]~4 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[3]~3 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[2]~2 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[1]~1 ,
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|ram_read_address[0]~0 }),
	.portbdataout({
\float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|q_b[204] }));
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .operation_mode = "dual_port";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .ram_block_type = "M10K";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .mixed_port_feed_through_mode = "dont_care";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .logical_ram_name = "float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ALTSYNCRAM";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .data_interleave_width_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .data_interleave_offset_in_bits = 1;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_logical_ram_depth = 32;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_logical_ram_width = 297;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_address_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_data_out_clock = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_data_out_clear = "none";
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_first_address = 0;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfifo:scfifo_component|scfifo_t6d1:auto_generated|a_dpfifo_n9a1:dpfifo|altsyncram_lkn1:FIFOram|ram_block1a204 .port_a_last_address = 31;
defparam \float_add_function:float_add_function_inst0|float_add_basic_block_1:float_add_basic_block_1|lsu_top:lsu_local_bb1_st_c0_exe1|lsu_bursting_write:bursting_write|lsu_bursting_write_internal:bursting_write|acl_data_fifo:req_fifo|acl_fifo:fifo_inner|scfif